RK3568学习笔记13：设备树
1. 设备树
设备树 (Device Tree)，将这个词分开就是“设备”和“树”，描述设备树的文件叫做DTS(Device Tree Source)，这个 DTS文件采用树形结构描述板级设备，也就是开发板上的设备信息，比如CPU数量、 内存基地址、 IIC接口上接了哪些设备、 SPI接口上接了哪些设备等等，如图
在上图中，树的主干就是系统总线， IIC控制器、 GPIO控制器、 SPI控制器等都是接到系统主线上的分支。 IIC控制器有分为 IIC1和 IIC2两种，其中 IIC1上接了FT5206和 AT24C02这两个 IIC设备， IIC2上只接了 MPU6050这个设备。
DTS文件的主要功能就是按照上图所示的结构来描述 板子上的设备信息， DTS文件描述设备信息是有相应的语法规则要求的。
ARM社区引入了 PowerPC等架构已经采用的设备树 (Flattened Device Tree)，将这些描述板级硬件信息的内容都从 Linux内中分离开来，用一个专属的文件格式来描
述，这个专属的文件就叫做设备树，文件扩展名为 .dts。一个 SOC可以作出很多不同的板子，这些不同的板子肯定是有共同的信息，将这些共同的信息提取出来作为一个通用的文件，其他的 .dts文件直接引用这个通用文件即可，这个通用文件就是 .dtsi文件，类似于 C语言中的头文件。一般 .dts描述板级信息 (也就是开发板上有哪些 IIC设备、 SPI设备等 ).dtsi描述 SOC级信息 (也就是 SOC有几个 CPU、主频是多少、各个外设控制器信息等 )。
2. DTS,DTB,DTC
这两个文件是什么关系呢？ DTS是设备树源码文件， DTB是将DTS编译以后得到的二进制文件。将 .c文件编译为 .o需要用到 gcc编译器，那么将 .dts编译为 .dtb需要用到 DTC工具！ DTC工具源码在 Linux内核的 scripts/dtc目录下，scripts/dtc/Makefile 文件，内容如下：
# SPDX-License-Identifier: GPL-2.0
# scripts/dtc makefile
hostprogs-y := dtc
always := $(hostprogs-y)
dtc-objs := dtc.o flattree.o fstree.o data.o livetree.o treesource.o \
srcpos.o checks.o util.o
dtc-objs += dtc-lexer.lex.o dtc-parser.tab.o
# Source files need to get at the userspace version of libfdt_env.h to compile
HOST_EXTRACFLAGS := -I$(src)/libfdt
# Generated files need one more search path to include headers in source tree
HOSTCFLAGS_dtc-lexer.lex.o := -I$(src)
HOSTCFLAGS_dtc-parser.tab.o := -I$(src)
# dependencies on generated files need to be listed explicitly
$(obj)/dtc-lexer.lex.o: $(obj)/dtc-parser.tab.h
可以看出，DTC工具依赖于 dtc.c、 flattree.c、 fstree.c等文件，最终编译并链接出 DTC这个主机文件。如果要编译 DTS文件的话只需要进入到 Linux源码根目录下，然后执行如下命令： ：(对于 RK3568，需要指定 ARCH=arm64)
make ARCH=arm64 all
或者
make ARCH=arm64 dtbs
输出如下
guo@DrGuo-Yoga:~/rk3568_linux_sdk/kernel$ make ARCH=arm64 all
scripts/kconfig/conf --syncconfig Kconfig
CALL scripts/checksyscalls.sh
CHK include/generated/compile.h
CC kernel/printk/printk.o
AR kernel/printk/built-in.a
GZIP kernel/config_data.gz
UPD kernel/config_data.h
CC kernel/configs.o
AR kernel/built-in.a
GEN .version
CHK include/generated/compile.h
UPD include/generated/compile.h
CC init/version.o
AR init/built-in.a
AR built-in.a
MODPOST vmlinux.o
KSYM .tmp_kallsyms1.o
KSYM .tmp_kallsyms2.o
LD vmlinux
SORTEX vmlinux
SYSMAP System.map
OBJCOPY arch/arm64/boot/Image
GZIP arch/arm64/boot/Image.gz
DTC arch/arm64/boot/dts/rockchip/px30-ad-d6-anx6345.dtb
DTC arch/arm64/boot/dts/rockchip/px30-ad-r35-mb-rk618-dual-lvds.dtb
DTC arch/arm64/boot/dts/rockchip/px30-ad-r35-mb-rk618-hdmi.dtb
DTC arch/arm64/boot/dts/rockchip/px30-ad-r35-mb-rk618-hdmi-lvds.dtb
DTC arch/arm64/boot/dts/rockchip/px30-ad-r35-mb-rk618-lvds.dtb
DTC arch/arm64/boot/dts/rockchip/px30-evb-ddr3-lvds-v10.dtb
DTC arch/arm64/boot/dts/rockchip/px30-evb-ddr3-v10.dtb
DTC arch/arm64/boot/dts/rockchip/px30-evb-ddr3-v10-avb.dtb
DTC arch/arm64/boot/dts/rockchip/px30-evb-ddr3-v10-linux.dtb
DTC arch/arm64/boot/dts/rockchip/px30-evb-ddr3-v10-robot-linux.dtb
DTC arch/arm64/boot/dts/rockchip/px30-evb-ddr3-v10-robot-no-gpu-linux.dtb
DTC arch/arm64/boot/dts/rockchip/px30-evb-ddr3-v11.dtb
DTC arch/arm64/boot/dts/rockchip/px30-evb-ddr3-v11-avb.dtb
DTC arch/arm64/boot/dts/rockchip/px30-evb-ddr3-v11-linux.dtb
DTC arch/arm64/boot/dts/rockchip/px30-evb-ddr4-v10.dtb
DTC arch/arm64/boot/dts/rockchip/px30-evb-ext-rk618.dtb
DTC arch/arm64/boot/dts/rockchip/px30-evb-ext-rk618-avb.dtb
DTC arch/arm64/boot/dts/rockchip/px30-z7-a0-rk618-dsi.dtb
DTC arch/arm64/boot/dts/rockchip/rk3326-evb-ai-va-v10.dtb
DTC arch/arm64/boot/dts/rockchip/rk3326-evb-ai-va-v11.dtb
DTC arch/arm64/boot/dts/rockchip/rk3326-evb-ai-va-v11-i2s-dmic.dtb
DTC arch/arm64/boot/dts/rockchip/rk3326-evb-ai-va-v12.dtb
DTC arch/arm64/boot/dts/rockchip/rk3326-evb-lp3-v10.dtb
DTC arch/arm64/boot/dts/rockchip/rk3326-evb-lp3-v10-avb.dtb
DTC arch/arm64/boot/dts/rockchip/rk3326-evb-lp3-v10-linux.dtb
DTC arch/arm64/boot/dts/rockchip/rk3326-evb-lp3-v10-robot-linux.dtb
DTC arch/arm64/boot/dts/rockchip/rk3326-evb-lp3-v10-robot-no-gpu-linux.dtb
DTC arch/arm64/boot/dts/rockchip/rk3326-evb-lp3-v11.dtb
DTC arch/arm64/boot/dts/rockchip/rk3326-evb-lp3-v11-avb.dtb
DTC arch/arm64/boot/dts/rockchip/rk3326-evb-lp3-v12-linux.dtb
DTC arch/arm64/boot/dts/rockchip/rk3326-863-lp3-v10.dtb
DTC arch/arm64/boot/dts/rockchip/rk3326-863-lp3-v10-avb.dtb
DTC arch/arm64/boot/dts/rockchip/rk3326-863-lp3-v10-rkisp1.dtb
DTC arch/arm64/boot/dts/rockchip/rk3326-86v-v10.dtb
DTC arch/arm64/boot/dts/rockchip/rk3328-box-liantong.dtb
DTC arch/arm64/boot/dts/rockchip/rk3328-box-liantong-avb.dtb
DTC arch/arm64/boot/dts/rockchip/rk3328-evb.dtb
DTC arch/arm64/boot/dts/rockchip/rk3328-evb-android.dtb
DTC arch/arm64/boot/dts/rockchip/rk3328-evb-android-avb.dtb
DTC arch/arm64/boot/dts/rockchip/rk3328-rock64.dtb
DTC arch/arm64/boot/dts/rockchip/rk3328-rock64-android.dtb
DTC arch/arm64/boot/dts/rockchip/rk3328-rock64-android-avb.dtb
DTC arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dtb
DTC arch/arm64/boot/dts/rockchip/rk3358-evb-ddr3-v10-linux.dtb
DTC arch/arm64/boot/dts/rockchip/rk3358m-vehicle-v10.dtb
DTC arch/arm64/boot/dts/rockchip/rk3368-808-evb.dtb
DTC arch/arm64/boot/dts/rockchip/rk3368-evb-act8846.dtb
DTC arch/arm64/boot/dts/rockchip/rk3368-geekbox.dtb
DTC arch/arm64/boot/dts/rockchip/rk3368-lion-haikou.dtb
DTC arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dtb
DTC arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dtb
DTC arch/arm64/boot/dts/rockchip/rk3368-r88.dtb
DTC arch/arm64/boot/dts/rockchip/rk3368-tablet.dtb
DTC arch/arm64/boot/dts/rockchip/rk3368a-817-tablet.dtb
DTC arch/arm64/boot/dts/rockchip/rk3368a-817-tablet-bnd.dtb
DTC arch/arm64/boot/dts/rockchip/rk3399-evb.dtb
DTC arch/arm64/boot/dts/rockchip/rk3399-evb-ind-lpddr4-android.dtb
DTC arch/arm64/boot/dts/rockchip/rk3399-evb-ind-lpddr4-android-avb.dtb
DTC arch/arm64/boot/dts/rockchip/rk3399-evb-ind-lpddr4-linux.dtb
DTC arch/arm64/boot/dts/rockchip/rk3399-evb-ind-lpddr4-v13-android-avb.dtb
DTC arch/arm64/boot/dts/rockchip/rk3399-ficus.dtb
DTC arch/arm64/boot/dts/rockchip/rk3399-firefly.dtb
DTC arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dtb
DTC arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtb
DTC arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dtb
DTC arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator-edp-avb.dtb
DTC arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator-linux.dtb
DTC arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator-lp4-linux.dtb
DTC arch/arm64/boot/dts/rockchip/rk3399-tve1030g-avb.dtb
DTC arch/arm64/boot/dts/rockchip/rk3399pro-evb-lp4-v11-linux.dtb
DTC arch/arm64/boot/dts/rockchip/rk3399pro-evb-v10-linux.dtb
DTC arch/arm64/boot/dts/rockchip/rk3399pro-evb-v11-linux.dtb
DTC arch/arm64/boot/dts/rockchip/rk3399pro-evb-v14-linux.dtb
DTC arch/arm64/boot/dts/rockchip/rk3566-box-demo-v10.dtb
DTC arch/arm64/boot/dts/rockchip/rk3566-box-demo-v10-android9.dtb
DTC arch/arm64/boot/dts/rockchip/rk3566-evb-mipitest-v10.dtb
DTC arch/arm64/boot/dts/rockchip/rk3566-evb1-ddr4-v10.dtb
DTC arch/arm64/boot/dts/rockchip/rk3566-evb1-ddr4-v10-linux.dtb
DTC arch/arm64/boot/dts/rockchip/rk3566-evb1-ddr4-v10-lvds.dtb
DTC arch/arm64/boot/dts/rockchip/rk3566-evb2-lp4x-v10.dtb
DTC arch/arm64/boot/dts/rockchip/rk3566-evb2-lp4x-v10-edp.dtb
DTC arch/arm64/boot/dts/rockchip/rk3566-evb2-lp4x-v10-eink.dtb
DTC arch/arm64/boot/dts/rockchip/rk3566-evb2-lp4x-v10-i2s-mic-array.dtb
arch/arm64/boot/dts/rockchip/rk3566-evb2-lp4x-v10-i2s-mic-array.dtb: Warning (sound_dai_property): /rk809-sound/simple-audio-card,codec:sound-dai: property size (4) too small for cell size 1
DTC arch/arm64/boot/dts/rockchip/rk3566-evb2-lp4x-v10-linux.dtb
DTC arch/arm64/boot/dts/rockchip/rk3566-evb2-lp4x-v10-pdm-mic-array.dtb
arch/arm64/boot/dts/rockchip/rk3566-evb2-lp4x-v10-pdm-mic-array.dtb: Warning (sound_dai_property): /rk809-sound/simple-audio-card,codec:sound-dai: property size (4) too small for cell size 1
DTC arch/arm64/boot/dts/rockchip/rk3566-evb3-ddr3-v10.dtb
DTC arch/arm64/boot/dts/rockchip/rk3566-evb3-ddr3-v10-linux.dtb
DTC arch/arm64/boot/dts/rockchip/rk3566-evb5-lp4x-v10.dtb
DTC arch/arm64/boot/dts/rockchip/rk3566-rk817-eink.dtb
DTC arch/arm64/boot/dts/rockchip/rk3566-rk817-eink-w6.dtb
DTC arch/arm64/boot/dts/rockchip/rk3566-rk817-eink-w103.dtb
DTC arch/arm64/boot/dts/rockchip/rk3566-rk817-tablet.dtb
DTC arch/arm64/boot/dts/rockchip/rk3566-rk817-tablet-k108.dtb
DTC arch/arm64/boot/dts/rockchip/rk3566-rk817-tablet-rkg11.dtb
DTC arch/arm64/boot/dts/rockchip/rk3566-rk817-tablet-v10.dtb
DTC arch/arm64/boot/dts/rockchip/rk3568-evb1-ddr4-v10.dtb
DTC arch/arm64/boot/dts/rockchip/rk3568-evb1-ddr4-v10-android9.dtb
DTC arch/arm64/boot/dts/rockchip/rk3568-evb1-ddr4-v10-linux.dtb
DTC arch/arm64/boot/dts/rockchip/rk3568-evb1-ddr4-v10-linux-spi-nor.dtb
DTC arch/arm64/boot/dts/rockchip/rk3568-evb2-lp4x-v10.dtb
DTC arch/arm64/boot/dts/rockchip/rk3568-evb2-lp4x-v10-bt1120-to-hdmi.dtb
DTC arch/arm64/boot/dts/rockchip/rk3568-evb4-lp3-v10.dtb
DTC arch/arm64/boot/dts/rockchip/rk3568-evb5-ddr4-v10.dtb
DTC arch/arm64/boot/dts/rockchip/rk3568-evb6-ddr3-v10.dtb
DTC arch/arm64/boot/dts/rockchip/rk3568-evb6-ddr3-v10-linux.dtb
DTC arch/arm64/boot/dts/rockchip/rk3568-evb6-ddr3-v10-rk628-bt1120-to-hdmi.dtb
DTC arch/arm64/boot/dts/rockchip/rk3568-evb6-ddr3-v10-rk628-rgb2hdmi.dtb
DTC arch/arm64/boot/dts/rockchip/rk3568-evb6-ddr3-v10-rk630-bt656-to-cvbs.dtb
DTC arch/arm64/boot/dts/rockchip/rk3568-evb7-ddr4-v10.dtb
DTC arch/arm64/boot/dts/rockchip/rk3568-iotest-ddr3-v10.dtb
DTC arch/arm64/boot/dts/rockchip/rk3568-iotest-ddr3-v10-linux.dtb
DTC arch/arm64/boot/dts/rockchip/rk3568-nvr-demo-v10.dtb
DTC arch/arm64/boot/dts/rockchip/rk3568-nvr-demo-v10-linux.dtb
DTC arch/arm64/boot/dts/rockchip/rk3568-nvr-demo-v10-linux-spi-nand.dtb
DTC arch/arm64/boot/dts/rockchip/rk3568-nvr-demo-v12-linux.dtb
DTC arch/arm64/boot/dts/rockchip/rk3568-nvr-demo-v12-linux-spi-nand.dtb
DTC arch/arm64/boot/dts/rockchip/rk630-rk3568-ddr3-v10.dtb
Building modules, stage 2.
MODPOST 4 modules
make ARCH=arm64 all 命令是编译 Linux源码中的所有东西，包括 uImage/zImage，.ko驱动模块以及设备树，
如果只是编译设备树的话建议使用 make ARCH=arm64 dtbs 命令 make ARCH=arm64 dtbs会编译选中的所有设备树文件。
如果只要编译指定的某个设备树，比如 我们 ATK-DLRK3568开发板对应的 rk3568-atk-evb1-ddr4-v10-linux.dts”，可以输入如下命令
make ARCH=arm64 rockchip/rk3568-atk-evb1-ddr4-v10-linux.dtb
基于ARM架构的 SOC有很多种，一种 SOC又可以制作出很多款板子，每个板子都有一个对应的 DTS文件，那么如何确定编译哪一个 DTS文件呢？我们就以 RK3568这款芯片对应的板子为例来看一下，打开arch/arm64/boot/dts/rockchip/Makefile，内容如下：
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-ad-d6-anx6345.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-ad-r35-mb-rk618-dual-lvds.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-ad-r35-mb-rk618-hdmi.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-ad-r35-mb-rk618-hdmi-lvds.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-ad-r35-mb-rk618-lvds.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-evb-ddr3-lvds-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-evb-ddr3-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-evb-ddr3-v10-avb.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-evb-ddr3-v10-linux.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-evb-ddr3-v10-robot-linux.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-evb-ddr3-v10-robot-no-gpu-linux.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-evb-ddr3-v11.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-evb-ddr3-v11-avb.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-evb-ddr3-v11-linux.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-evb-ddr4-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-evb-ext-rk618.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-evb-ext-rk618-avb.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-z7-a0-rk618-dsi.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-evb-ai-va-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-evb-ai-va-v11.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-evb-ai-va-v11-i2s-dmic.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-evb-ai-va-v12.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-evb-lp3-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-evb-lp3-v10-avb.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-evb-lp3-v10-linux.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-evb-lp3-v10-robot-linux.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-evb-lp3-v10-robot-no-gpu-linux.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-evb-lp3-v11.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-evb-lp3-v11-avb.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-evb-lp3-v12-linux.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-863-lp3-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-863-lp3-v10-avb.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-863-lp3-v10-rkisp1.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-86v-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-box-liantong.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-box-liantong-avb.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb-android.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb-android-avb.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64-android.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64-android-avb.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3358-evb-ddr3-v10-linux.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3358m-vehicle-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-808-evb.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-evb-act8846.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-geekbox.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-lion-haikou.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-orion-r68-meta.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-px5-evb.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-r88.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-tablet.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368a-817-tablet.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368a-817-tablet-bnd.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-evb.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-evb-ind-lpddr4-android.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-evb-ind-lpddr4-android-avb.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-evb-ind-lpddr4-linux.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-evb-ind-lpddr4-v13-android-avb.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-ficus.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-firefly.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-puma-haikou.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire-excavator.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire-excavator-edp-avb.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire-excavator-linux.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire-excavator-lp4-linux.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-tve1030g-avb.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399pro-evb-lp4-v11-linux.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399pro-evb-v10-linux.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399pro-evb-v11-linux.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399pro-evb-v14-linux.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-box-demo-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-box-demo-v10-android9.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-evb-mipitest-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-evb1-ddr4-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-evb1-ddr4-v10-linux.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-evb1-ddr4-v10-lvds.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-evb2-lp4x-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-evb2-lp4x-v10-edp.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-evb2-lp4x-v10-eink.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-evb2-lp4x-v10-i2s-mic-array.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-evb2-lp4x-v10-linux.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-evb2-lp4x-v10-pdm-mic-array.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-evb3-ddr3-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-evb3-ddr3-v10-linux.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-evb5-lp4x-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-rk817-eink.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-rk817-eink-w6.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-rk817-eink-w103.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-rk817-tablet.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-rk817-tablet-k108.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-rk817-tablet-rkg11.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-rk817-tablet-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-ddr4-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-ddr4-v10-android9.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-ddr4-v10-linux.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-ddr4-v10-linux-spi-nor.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb2-lp4x-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb2-lp4x-v10-bt1120-to-hdmi.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb4-lp3-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb5-ddr4-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb6-ddr3-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb6-ddr3-v10-linux.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb6-ddr3-v10-rk628-bt1120-to-hdmi.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb6-ddr3-v10-rk628-rgb2hdmi.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb6-ddr3-v10-rk630-bt656-to-cvbs.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb7-ddr4-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-iotest-ddr3-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-iotest-ddr3-v10-linux.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nvr-demo-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nvr-demo-v10-linux.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nvr-demo-v10-linux-spi-nand.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nvr-demo-v12-linux.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nvr-demo-v12-linux-spi-nand.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-atk-evb1-ddr4-v10-linux.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk630-rk3568-ddr3-v10.dtb
可以看出 ，比如 这个 Makefile下有许多 RK3326、 RK3566、 RK3568等不同的 .dtb文件 。如果我们使用 RK3568新做了一个板子，只需要新建一个此板子对应的 .dts文件，然后将对应的 .dtb文件名添加到 这个 Makefile下，这样在编译设备树的时候就会将对应的 .dts编译为二进制的 .dtb文件。
3. DTS语法
语法。关于设备树详细的语法规则请参考《 Devicetree SpecificationV0.2.pdf》和
《 Power_ePAPR_APPROVED_v1.12.pdf》这两份文档。路径：开发板光盘 06、参考资料 Devicetree SpecificationV0. SpecificationV0.2.pdf以及Power_ePAPR_APPROVED_v1.12.pdf
3.1 dtsi 头文件
和C语言一样，设备树也支持头文件，设备树的头文件扩展名为 .dtsi。在 rk3568-atk-evb1-ddr4-v10-linux.dts中有如下所示内容：
#include "rk3568-atk-evb1-ddr4-v10.dtsi"
#include "rk3568-linux.dtsi"
#include "rk3568-screen_choose.dtsi"
#include "rk3568-lcds.dtsi"
设备树中除了引用dtsi文件外，还可以引用.h头文件，rk3568.dtsi中引用了如下头文件
#include <dt-bindings/clock/rk3568-cru.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/soc/rockchip,boot-mode.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/power/rk3568-power.h>
#include <dt-bindings/soc/rockchip-system-status.h>
#include <dt-bindings/suspend/rockchip-rk3568.h>
#include <dt-bindings/thermal/thermal.h>
一般 .dtsi文件用于描述 SOC的内部外设信息，比如 CPU架构、主频、外设寄存器地址范围，比如 UART、 IIC等等。 比如 rk3568.dtsi就是描述 RK3568芯片本身的外设信息，如下所示：
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2020 Rockchip Electronics Co., Ltd.
*/
#include <dt-bindings/clock/rk3568-cru.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/soc/rockchip,boot-mode.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/power/rk3568-power.h>
#include <dt-bindings/soc/rockchip-system-status.h>
#include <dt-bindings/suspend/rockchip-rk3568.h>
#include <dt-bindings/thermal/thermal.h>
#include "rk3568-dram-default-timing.dtsi"
/ {
compatible = "rockchip,rk3568";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
aliases {
csi2dphy0 = &csi2_dphy0;
csi2dphy1 = &csi2_dphy1;
csi2dphy2 = &csi2_dphy2;
dsi0 = &dsi0;
dsi1 = &dsi1;
ethernet0 = &gmac0;
ethernet1 = &gmac1;
gpio0 = &gpio0;
gpio1 = &gpio1;
gpio2 = &gpio2;
gpio3 = &gpio3;
gpio4 = &gpio4;
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c4;
i2c5 = &i2c5;
mmc0 = &sdhci;
mmc1 = &sdmmc0;
mmc2 = &sdmmc1;
mmc3 = &sdmmc2;
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
serial3 = &uart3;
serial4 = &uart4;
serial5 = &uart5;
serial6 = &uart6;
serial7 = &uart7;
serial8 = &uart8;
serial9 = &uart9;
spi0 = &spi0;
spi1 = &spi1;
spi2 = &spi2;
spi3 = &spi3;
spi4 = &sfc; // for U-Boot
};
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x0>;
enable-method = "psci";
clocks = <&scmi_clk 0>;
operating-points-v2 = <&cpu0_opp_table>;
cpu-idle-states = <&CPU_SLEEP>;
#cooling-cells = <2>;
dynamic-power-coefficient = <187>;
};
cpu1: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x100>;
enable-method = "psci";
clocks = <&scmi_clk 0>;
operating-points-v2 = <&cpu0_opp_table>;
cpu-idle-states = <&CPU_SLEEP>;
};
cpu2: cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x200>;
enable-method = "psci";
clocks = <&scmi_clk 0>;
operating-points-v2 = <&cpu0_opp_table>;
cpu-idle-states = <&CPU_SLEEP>;
};
cpu3: cpu@300 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x300>;
enable-method = "psci";
clocks = <&scmi_clk 0>;
operating-points-v2 = <&cpu0_opp_table>;
cpu-idle-states = <&CPU_SLEEP>;
};
idle-states {
entry-method = "psci";
CPU_SLEEP: cpu-sleep {
compatible = "arm,idle-state";
local-timer-stop;
arm,psci-suspend-param = <0x0010000>;
entry-latency-us = <100>;
exit-latency-us = <120>;
min-residency-us = <1000>;
};
};
};
cpu0_opp_table: cpu0-opp-table {
compatible = "operating-points-v2";
opp-shared;
mbist-vmin = <825000 900000 950000>;
nvmem-cells = <&cpu_leakage>, <&core_pvtm>, <&mbist_vmin>;
nvmem-cell-names = "leakage", "pvtm", "mbist-vmin";
rockchip,pvtm-voltage-sel = <
0 84000 0
84001 91000 1
91001 100000 2
>;
rockchip,pvtm-freq = <408000>;
rockchip,pvtm-volt = <900000>;
rockchip,pvtm-ch = <0 5>;
rockchip,pvtm-sample-time = <1000>;
rockchip,pvtm-number = <10>;
rockchip,pvtm-error = <1000>;
rockchip,pvtm-ref-temp = <40>;
rockchip,pvtm-temp-prop = <26 26>;
rockchip,thermal-zone = "soc-thermal";
rockchip,temp-hysteresis = <5000>;
rockchip,low-temp = <0>;
rockchip,low-temp-adjust-volt = <
/* MHz MHz uV */
0 1608 75000
>;
opp-408000000 {
opp-hz = /bits/ 64 <408000000>;
opp-microvolt = <850000 850000 1150000>;
opp-microvolt-L0 = <850000 850000 1150000>;
opp-microvolt-L1 = <825000 825000 1150000>;
opp-microvolt-L2 = <825000 825000 1150000>;
clock-latency-ns = <40000>;
};
opp-600000000 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <850000 825000 1150000>;
opp-microvolt-L0 = <850000 850000 1150000>;
opp-microvolt-L1 = <825000 825000 1150000>;
opp-microvolt-L2 = <825000 825000 1150000>;
clock-latency-ns = <40000>;
};
opp-816000000 {
opp-hz = /bits/ 64 <816000000>;
opp-microvolt = <850000 850000 1150000>;
opp-microvolt-L0 = <850000 850000 1150000>;
opp-microvolt-L1 = <825000 825000 1150000>;
opp-microvolt-L2 = <825000 825000 1150000>;
clock-latency-ns = <40000>;
opp-suspend;
};
opp-1104000000 {
opp-hz = /bits/ 64 <1104000000>;
opp-microvolt = <900000 900000 1150000>;
opp-microvolt-L0 = <900000 900000 1150000>;
opp-microvolt-L1 = <825000 825000 1150000>;
opp-microvolt-L2 = <825000 825000 1150000>;
clock-latency-ns = <40000>;
};
opp-1416000000 {
opp-hz = /bits/ 64 <1416000000>;
opp-microvolt = <1000000 1000000 1150000>;
opp-microvolt-L0 = <1000000 1000000 1150000>;
opp-microvolt-L1 = <925000 925000 1150000>;
opp-microvolt-L2 = <925000 925000 1150000>;
clock-latency-ns = <40000>;
};
opp-1608000000 {
opp-hz = /bits/ 64 <1608000000>;
opp-microvolt = <1075000 1075000 1150000>;
opp-microvolt-L0 = <1075000 1075000 1150000>;
opp-microvolt-L1 = <1000000 1000000 1150000>;
opp-microvolt-L2 = <1000000 1000000 1150000>;
clock-latency-ns = <40000>;
};
opp-1800000000 {
opp-hz = /bits/ 64 <1800000000>;
opp-microvolt = <1125000 1125000 1150000>;
opp-microvolt-L0 = <1125000 1125000 1150000>;
opp-microvolt-L1 = <1050000 1050000 1150000>;
opp-microvolt-L2 = <1050000 1050000 1150000>;
clock-latency-ns = <40000>;
};
opp-1992000000 {
opp-hz = /bits/ 64 <1992000000>;
opp-microvolt = <1150000 1150000 1150000>;
opp-microvolt-L0 = <1150000 1150000 1150000>;
opp-microvolt-L1 = <1100000 1100000 1150000>;
opp-microvolt-L2 = <1075000 1075000 1150000>;
clock-latency-ns = <40000>;
};
};
arm-pmu {
compatible = "arm,cortex-a55-pmu", "arm,armv8-pmuv3";
interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
};
cpuinfo {
compatible = "rockchip,cpuinfo";
nvmem-cells = <&otp_id>, <&otp_cpu_version>, <&cpu_code>;
nvmem-cell-names = "id", "cpu-version", "cpu-code";
};
display_subsystem: display-subsystem {
compatible = "rockchip,display-subsystem";
memory-region = <&drm_logo>, <&drm_cubic_lut>;
memory-region-names = "drm-logo", "drm-cubic-lut";
ports = <&vop_out>;
devfreq = <&dmc>;
route {
route_dsi0: route-dsi0 {
status = "disabled";
logo,uboot = "logo.bmp";
logo,kernel = "logo_kernel.bmp";
logo,mode = "center";
charge_logo,mode = "center";
connect = <&vp0_out_dsi0>;
};
route_dsi1: route-dsi1 {
status = "disabled";
logo,uboot = "logo.bmp";
logo,kernel = "logo_kernel.bmp";
logo,mode = "center";
charge_logo,mode = "center";
connect = <&vp0_out_dsi1>;
};
route_edp: route-edp {
status = "disabled";
logo,uboot = "logo.bmp";
logo,kernel = "logo_kernel.bmp";
logo,mode = "center";
charge_logo,mode = "center";
connect = <&vp0_out_edp>;
};
route_hdmi: route-hdmi {
status = "disabled";
logo,uboot = "logo.bmp";
logo,kernel = "logo_kernel.bmp";
logo,mode = "center";
charge_logo,mode = "center";
connect = <&vp1_out_hdmi>;
};
route_lvds: route-lvds {
status = "disabled";
logo,uboot = "logo.bmp";
logo,kernel = "logo_kernel.bmp";
logo,mode = "center";
charge_logo,mode = "center";
connect = <&vp1_out_lvds>;
};
route_rgb: route-rgb {
status = "disabled";
logo,uboot = "logo.bmp";
logo,kernel = "logo_kernel.bmp";
logo,mode = "center";
charge_logo,mode = "center";
connect = <&vp2_out_rgb>;
};
};
};
firmware {
optee: optee {
compatible = "linaro,optee-tz";
method = "smc";
};
scmi: scmi {
compatible = "arm,scmi-smc";
shmem = <&scmi_shmem>;
arm,smc-id = <0x82000010>;
#address-cells = <1>;
#size-cells = <0>;
scmi_clk: protocol@14 {
reg = <0x14>;
#clock-cells = <1>;
rockchip,clk-init = <1416000000>;
};
};
sdei: sdei {
compatible = "arm,sdei-1.0";
method = "smc";
};
};
mpp_srv: mpp-srv {
compatible = "rockchip,mpp-service";
rockchip,taskqueue-count = <6>;
rockchip,resetgroup-count = <6>;
status = "disabled";
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
reserved_memory: reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
drm_logo: drm-logo@00000000 {
compatible = "rockchip,drm-logo";
reg = <0x0 0x0 0x0 0x0>;
};
drm_cubic_lut: drm-cubic-lut@00000000 {
compatible = "rockchip,drm-cubic-lut";
reg = <0x0 0x0 0x0 0x0>;
};
};
rockchip_suspend: rockchip-suspend {
compatible = "rockchip,pm-rk3568";
status = "disabled";
rockchip,sleep-debug-en = <1>;
rockchip,sleep-mode-config = <
(0
| RKPM_SLP_ARMOFF_LOGOFF
| RKPM_SLP_CENTER_OFF
| RKPM_SLP_HW_PLLS_OFF
| RKPM_SLP_PMUALIVE_32K
| RKPM_SLP_OSC_DIS
| RKPM_SLP_PMIC_LP
| RKPM_SLP_32K_PVTM
)
>;
rockchip,wakeup-config = <
(0
| RKPM_GPIO_WKUP_EN
)
>;
};
rockchip_system_monitor: rockchip-system-monitor {
compatible = "rockchip,system-monitor";
rockchip,thermal-zone = "soc-thermal";
};
thermal_zones: thermal-zones {
soc_thermal: soc-thermal {
polling-delay-passive = <20>; /* milliseconds */
polling-delay = <1000>; /* milliseconds */
sustainable-power = <905>; /* milliwatts */
thermal-sensors = <&tsadc 0>;
trips {
threshold: trip-point-0 {
temperature = <75000>;
hysteresis = <2000>;
type = "passive";
};
target: trip-point-1 {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
soc_crit: soc-crit {
/* millicelsius */
temperature = <115000>;
/* millicelsius */
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&target>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
contribution = <1024>;
};
map1 {
trip = <&target>;
cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
contribution = <1024>;
};
};
};
gpu_thermal: gpu-thermal {
polling-delay-passive = <20>; /* milliseconds */
polling-delay = <1000>; /* milliseconds */
thermal-sensors = <&tsadc 1>;
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
arm,no-tick-in-suspend;
};
gmac0_clkin: external-gmac0-clock {
compatible = "fixed-clock";
clock-frequency = <125000000>;
clock-output-names = "gmac0_clkin";
#clock-cells = <0>;
};
gmac1_clkin: external-gmac1-clock {
compatible = "fixed-clock";
clock-frequency = <125000000>;
clock-output-names = "gmac1_clkin";
#clock-cells = <0>;
};
gmac0_xpcsclk: xpcs-gmac0-clock {
compatible = "fixed-clock";
clock-frequency = <125000000>;
clock-output-names = "clk_gmac0_xpcs_mii";
#clock-cells = <0>;
};
gmac1_xpcsclk: xpcs-gmac1-clock {
compatible = "fixed-clock";
clock-frequency = <125000000>;
clock-output-names = "clk_gmac1_xpcs_mii";
#clock-cells = <0>;
};
i2s1_mclkin_rx: i2s1-mclkin-rx {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <12288000>;
clock-output-names = "i2s1_mclkin_rx";
};
i2s1_mclkin_tx: i2s1-mclkin-tx {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <12288000>;
clock-output-names = "i2s1_mclkin_tx";
};
i2s2_mclkin: i2s2-mclkin {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <12288000>;
clock-output-names = "i2s2_mclkin";
};
i2s3_mclkin: i2s3-mclkin {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <12288000>;
clock-output-names = "i2s3_mclkin";
};
mpll: mpll {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <800000000>;
clock-output-names = "mpll";
};
xin24m: xin24m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
clock-output-names = "xin24m";
};
xin32k: xin32k {
compatible = "fixed-clock";
clock-frequency = <32768>;
clock-output-names = "xin32k";
#clock-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&clk32k_out0>;
};
scmi_shmem: scmi-shmem@10f000 {
compatible = "arm,scmi-shmem";
reg = <0x0 0x0010f000 0x0 0x100>;
};
sata0: sata@fc000000 {
compatible = "snps,dwc-ahci";
reg = <0 0xfc000000 0 0x1000>;
clocks = <&cru ACLK_SATA0>, <&cru CLK_SATA0_PMALIVE>,
<&cru CLK_SATA0_RXOOB>;
clock-names = "sata", "pmalive", "rxoob";
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hostc";
phys = <&combphy0_us PHY_TYPE_SATA>;
phy-names = "sata-phy";
ports-implemented = <0x1>;
power-domains = <&power RK3568_PD_PIPE>;
status = "disabled";
};
sata1: sata@fc400000 {
compatible = "snps,dwc-ahci";
reg = <0 0xfc400000 0 0x1000>;
clocks = <&cru ACLK_SATA1>, <&cru CLK_SATA1_PMALIVE>,
<&cru CLK_SATA1_RXOOB>;
clock-names = "sata", "pmalive", "rxoob";
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hostc";
phys = <&combphy1_usq PHY_TYPE_SATA>;
phy-names = "sata-phy";
ports-implemented = <0x1>;
power-domains = <&power RK3568_PD_PIPE>;
status = "disabled";
};
sata2: sata@fc800000 {
compatible = "snps,dwc-ahci";
reg = <0 0xfc800000 0 0x1000>;
clocks = <&cru ACLK_SATA2>, <&cru CLK_SATA2_PMALIVE>,
<&cru CLK_SATA2_RXOOB>;
clock-names = "sata", "pmalive", "rxoob";
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hostc";
phys = <&combphy2_psq PHY_TYPE_SATA>;
phy-names = "sata-phy";
ports-implemented = <0x1>;
power-domains = <&power RK3568_PD_PIPE>;
status = "disabled";
};
usbdrd30: usbdrd {
compatible = "rockchip,rk3568-dwc3", "rockchip,rk3399-dwc3";
clocks = <&cru CLK_USB3OTG0_REF>, <&cru CLK_USB3OTG0_SUSPEND>,
<&cru ACLK_USB3OTG0>, <&cru PCLK_PIPE>;
clock-names = "ref_clk", "suspend_clk",
"bus_clk", "pipe_clk";
#address-cells = <2>;
#size-cells = <2>;
ranges;
status = "disabled";
usbdrd_dwc3: dwc3@fcc00000 {
compatible = "snps,dwc3";
reg = <0x0 0xfcc00000 0x0 0x400000>;
interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
dr_mode = "otg";
phys = <&u2phy0_otg>, <&combphy0_us PHY_TYPE_USB3>;
phy-names = "usb2-phy", "usb3-phy";
phy_type = "utmi_wide";
power-domains = <&power RK3568_PD_PIPE>;
resets = <&cru SRST_USB3OTG0>;
reset-names = "usb3-otg";
snps,dis_enblslpm_quirk;
snps,dis-u1u2-quirk;
snps,dis-u2-freeclk-exists-quirk;
snps,dis-del-phy-power-chg-quirk;
snps,dis-tx-ipgap-linecheck-quirk;
snps,dis_rxdet_inp3_quirk;
snps,xhci-trb-ent-quirk;
status = "disabled";
};
};
usbhost30: usbhost {
compatible = "rockchip,rk3568-dwc3", "rockchip,rk3399-dwc3";
clocks = <&cru CLK_USB3OTG1_REF>, <&cru CLK_USB3OTG1_SUSPEND>,
<&cru ACLK_USB3OTG1>, <&cru PCLK_PIPE>;
clock-names = "ref_clk", "suspend_clk",
"bus_clk", "pipe_clk";
#address-cells = <2>;
#size-cells = <2>;
ranges;
status = "disabled";
usbhost_dwc3: dwc3@fd000000 {
compatible = "snps,dwc3";
reg = <0x0 0xfd000000 0x0 0x400000>;
interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
dr_mode = "host";
phys = <&u2phy0_host>, <&combphy1_usq PHY_TYPE_USB3>;
phy-names = "usb2-phy", "usb3-phy";
phy_type = "utmi_wide";
power-domains = <&power RK3568_PD_PIPE>;
resets = <&cru SRST_USB3OTG1>;
reset-names = "usb3-host";
snps,dis_enblslpm_quirk;
snps,dis-u2-freeclk-exists-quirk;
snps,dis-del-phy-power-chg-quirk;
snps,dis-tx-ipgap-linecheck-quirk;
snps,dis_rxdet_inp3_quirk;
snps,xhci-trb-ent-quirk;
status = "disabled";
};
};
gic: interrupt-controller@fd400000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
interrupt-controller;
reg = <0x0 0xfd400000 0 0x10000>, /* GICD */
<0x0 0xfd460000 0 0xc0000>; /* GICR */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
its: interrupt-controller@fd440000 {
compatible = "arm,gic-v3-its";
msi-controller;
#msi-cells = <1>;
reg = <0x0 0xfd440000 0x0 0x20000>;
};
};
usb_host0_ehci: usb@fd800000 {
compatible = "generic-ehci";
reg = <0x0 0xfd800000 0x0 0x40000>;
interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>,
<&cru PCLK_USB>, <&usb2phy1>;
clock-names = "usbhost", "arbiter", "pclk", "utmi";
phys = <&u2phy1_otg>;
phy-names = "usb2-phy";
status = "disabled";
};
usb_host0_ohci: usb@fd840000 {
compatible = "generic-ohci";
reg = <0x0 0xfd840000 0x0 0x40000>;
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>,
<&cru PCLK_USB>, <&usb2phy1>;
clock-names = "usbhost", "arbiter", "pclk", "utmi";
phys = <&u2phy1_otg>;
phy-names = "usb2-phy";
status = "disabled";
};
usb_host1_ehci: usb@fd880000 {
compatible = "generic-ehci";
reg = <0x0 0xfd880000 0x0 0x40000>;
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>,
<&cru PCLK_USB>, <&usb2phy1>;
clock-names = "usbhost", "arbiter", "pclk", "utmi";
phys = <&u2phy1_host>;
phy-names = "usb2-phy";
status = "disabled";
};
usb_host1_ohci: usb@fd8c0000 {
compatible = "generic-ohci";
reg = <0x0 0xfd8c0000 0x0 0x40000>;
interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>,
<&cru PCLK_USB>, <&usb2phy1>;
clock-names = "usbhost", "arbiter", "pclk", "utmi";
phys = <&u2phy1_host>;
phy-names = "usb2-phy";
status = "disabled";
};
xpcs: syscon@fda00000 {
compatible = "rockchip,rk3568-xpcs", "syscon";
reg = <0x0 0xfda00000 0x0 0x200000>;
status = "disabled";
};
pmugrf: syscon@fdc20000 {
compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd";
reg = <0x0 0xfdc20000 0x0 0x10000>;
pmu_io_domains: io-domains {
compatible = "rockchip,rk3568-pmu-io-voltage-domain";
status = "disabled";
};
reboot_mode: reboot-mode {
compatible = "syscon-reboot-mode";
offset = <0x200>;
mode-bootloader = <BOOT_BL_DOWNLOAD>;
mode-charge = <BOOT_CHARGING>;
mode-fastboot = <BOOT_FASTBOOT>;
mode-loader = <BOOT_BL_DOWNLOAD>;
mode-normal = <BOOT_NORMAL>;
mode-recovery = <BOOT_RECOVERY>;
mode-ums = <BOOT_UMS>;
mode-panic = <BOOT_PANIC>;
mode-watchdog = <BOOT_WATCHDOG>;
};
};
pipegrf: syscon@fdc50000 {
compatible = "rockchip,rk3568-pipegrf", "syscon";
reg = <0x0 0xfdc50000 0x0 0x1000>;
};
grf: syscon@fdc60000 {
compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd";
reg = <0x0 0xfdc60000 0x0 0x10000>;
io_domains: io-domains {
compatible = "rockchip,rk3568-io-voltage-domain";
status = "disabled";
};
lvds: lvds {
compatible = "rockchip,rk3568-lvds";
phys = <&video_phy0>;
phy-names = "phy";
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
lvds_in_vp1: endpoint@1 {
reg = <1>;
remote-endpoint = <&vp1_out_lvds>;
status = "disabled";
};
lvds_in_vp2: endpoint@2 {
reg = <2>;
remote-endpoint = <&vp2_out_lvds>;
status = "disabled";
};
};
};
};
rgb: rgb {
compatible = "rockchip,rk3568-rgb";
pinctrl-names = "default";
pinctrl-0 = <&lcdc_ctl>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
rgb_in_vp2: endpoint@2 {
reg = <2>;
remote-endpoint = <&vp2_out_rgb>;
status = "disabled";
};
};
};
};
};
pipe_phy_grf0: syscon@fdc70000 {
compatible = "rockchip,pipe-phy-grf", "syscon";
reg = <0x0 0xfdc70000 0x0 0x1000>;
};
pipe_phy_grf1: syscon@fdc80000 {
compatible = "rockchip,pipe-phy-grf", "syscon";
reg = <0x0 0xfdc80000 0x0 0x1000>;
};
pipe_phy_grf2: syscon@fdc90000 {
compatible = "rockchip,pipe-phy-grf", "syscon";
reg = <0x0 0xfdc90000 0x0 0x1000>;
};
usb2phy0_grf: syscon@fdca0000 {
compatible = "rockchip,rk3568-usb2phy-grf", "syscon";
reg = <0x0 0xfdca0000 0x0 0x8000>;
};
usb2phy1_grf: syscon@fdca8000 {
compatible = "rockchip,rk3568-usb2phy-grf", "syscon";
reg = <0x0 0xfdca8000 0x0 0x8000>;
};
edp_phy_grf: syscon@fdcb0000 {
compatible = "rockchip,rk3568-edp-phy-grf", "syscon", "simple-mfd";
reg = <0x0 0xfdcb0000 0x0 0x100>;
clocks = <&cru PCLK_EDPPHY_GRF>;
edp_phy: edp-phy {
compatible = "rockchip,rk3568-edp-phy";
clocks = <&pmucru XIN_OSC0_EDPPHY_G>;
clock-names = "refclk";
#phy-cells = <0>;
status = "disabled";
};
};
pcie30_phy_grf: syscon@fdcb8000 {
compatible = "rockchip,pcie30-phy-grf", "syscon";
reg = <0x0 0xfdcb8000 0x0 0x10000>;
};
sram: sram@fdcc0000 {
compatible = "mmio-sram";
reg = <0x0 0xfdcc0000 0x0 0xb000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0xfdcc0000 0xb000>;
/* start address and size should be 4k algin */
rkvdec_sram: rkvdec-sram@0 {
reg = <0x0 0xb000>;
};
};
pmucru: clock-controller@fdd00000 {
compatible = "rockchip,rk3568-pmucru";
reg = <0x0 0xfdd00000 0x0 0x1000>;
rockchip,grf = <&grf>;
rockchip,pmugrf = <&pmugrf>;
#clock-cells = <1>;
#reset-cells = <1>;
assigned-clocks = <&pmucru SCLK_32K_IOE>;
assigned-clock-parents = <&pmucru CLK_RTC_32K>;
};
cru: clock-controller@fdd20000 {
compatible = "rockchip,rk3568-cru";
reg = <0x0 0xfdd20000 0x0 0x1000>;
rockchip,grf = <&grf>;
#clock-cells = <1>;
#reset-cells = <1>;
assigned-clocks =
<&pmucru CLK_RTC_32K>, <&cru ACLK_RKVDEC_PRE>,
<&cru CLK_RKVDEC_CORE>, <&pmucru PLL_PPLL>,
<&pmucru PCLK_PMU>, <&cru PLL_CPLL>,
<&cru CPLL_500M>, <&cru CPLL_333M>,
<&cru CPLL_250M>, <&cru CPLL_125M>,
<&cru CPLL_100M>, <&cru CPLL_62P5M>,
<&cru CPLL_50M>, <&cru CPLL_25M>,
<&cru PLL_GPLL>,
<&cru ACLK_BUS>, <&cru PCLK_BUS>,
<&cru ACLK_TOP_HIGH>, <&cru ACLK_TOP_LOW>,
<&cru HCLK_TOP>, <&cru PCLK_TOP>,
<&cru ACLK_PERIMID>, <&cru HCLK_PERIMID>,
<&cru PLL_NPLL>, <&cru ACLK_PIPE>,
<&cru PCLK_PIPE>, <&cru CLK_I2S0_8CH_TX_SRC>,
<&cru CLK_I2S0_8CH_RX_SRC>, <&cru CLK_I2S1_8CH_TX_SRC>,
<&cru CLK_I2S1_8CH_RX_SRC>, <&cru CLK_I2S2_2CH_SRC>,
<&cru CLK_I2S2_2CH_SRC>, <&cru CLK_I2S3_2CH_RX_SRC>,
<&cru CLK_I2S3_2CH_TX_SRC>, <&cru MCLK_SPDIF_8CH_SRC>,
<&cru ACLK_VOP>;
assigned-clock-rates =
<32768>, <300000000>,
<300000000>, <200000000>,
<100000000>, <1000000000>,
<500000000>, <333000000>,
<250000000>, <125000000>,
<100000000>, <62500000>,
<50000000>, <25000000>,
<1188000000>,
<150000000>, <100000000>,
<500000000>, <400000000>,
<150000000>, <100000000>,
<300000000>, <150000000>,
<1200000000>, <400000000>,
<100000000>, <1188000000>,
<1188000000>, <1188000000>,
<1188000000>, <1188000000>,
<1188000000>, <1188000000>,
<1188000000>, <1188000000>,
<500000000>;
assigned-clock-parents =
<&pmucru CLK_RTC32K_FRAC>, <&cru PLL_GPLL>,
<&cru PLL_GPLL>;
};
i2c0: i2c@fdd40000 {
compatible = "rockchip,rk3399-i2c";
reg = <0x0 0xfdd40000 0x0 0x1000>;
clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>;
clock-names = "i2c", "pclk";
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&i2c0_xfer>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
uart0: serial@fdd50000 {
compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
reg = <0x0 0xfdd50000 0x0 0x100>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pmucru SCLK_UART0>, <&pmucru PCLK_UART0>;
clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
dmas = <&dmac0 0>, <&dmac0 1>;
pinctrl-names = "default";
pinctrl-0 = <&uart0_xfer>;
status = "disabled";
};
pwm0: pwm@fdd70000 {
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
reg = <0x0 0xfdd70000 0x0 0x10>;
#pwm-cells = <3>;
pinctrl-names = "active";
pinctrl-0 = <&pwm0m0_pins>;
clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
clock-names = "pwm", "pclk";
status = "disabled";
};
pwm1: pwm@fdd70010 {
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
reg = <0x0 0xfdd70010 0x0 0x10>;
#pwm-cells = <3>;
pinctrl-names = "active";
pinctrl-0 = <&pwm1m0_pins>;
clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
clock-names = "pwm", "pclk";
status = "disabled";
};
pwm2: pwm@fdd70020 {
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
reg = <0x0 0xfdd70020 0x0 0x10>;
#pwm-cells = <3>;
pinctrl-names = "active";
pinctrl-0 = <&pwm2m0_pins>;
clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
clock-names = "pwm", "pclk";
status = "disabled";
};
pwm3: pwm@fdd70030 {
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
reg = <0x0 0xfdd70030 0x0 0x10>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
#pwm-cells = <3>;
pinctrl-names = "active";
pinctrl-0 = <&pwm3_pins>;
clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
clock-names = "pwm", "pclk";
status = "disabled";
};
pmu: power-management@fdd90000 {
compatible = "rockchip,rk3568-pmu", "syscon", "simple-mfd";
reg = <0x0 0xfdd90000 0x0 0x1000>;
power: power-controller {
compatible = "rockchip,rk3568-power-controller";
#power-domain-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
/* These power domains are grouped by VD_NPU */
pd_npu@RK3568_PD_NPU {
reg = <RK3568_PD_NPU>;
clocks = <&cru ACLK_NPU_PRE>,
<&cru HCLK_NPU_PRE>,
<&cru PCLK_NPU_PRE>;
pm_qos = <&qos_npu>;
};
/* These power domains are grouped by VD_GPU */
pd_gpu@RK3568_PD_GPU {
reg = <RK3568_PD_GPU>;
clocks = <&cru ACLK_GPU_PRE>,
<&cru PCLK_GPU_PRE>;
pm_qos = <&qos_gpu>;
};
/* These power domains are grouped by VD_LOGIC */
pd_vi@RK3568_PD_VI {
reg = <RK3568_PD_VI>;
clocks = <&cru HCLK_VI>,
<&cru PCLK_VI>;
pm_qos = <&qos_isp>,
<&qos_vicap0>,
<&qos_vicap1>;
};
pd_vo@RK3568_PD_VO {
reg = <RK3568_PD_VO>;
clocks = <&cru HCLK_VO>,
<&cru PCLK_VO>,
<&cru ACLK_VOP_PRE>;
pm_qos = <&qos_hdcp>,
<&qos_vop_m0>,
<&qos_vop_m1>;
};
pd_rga@RK3568_PD_RGA {
reg = <RK3568_PD_RGA>;
clocks = <&cru HCLK_RGA_PRE>,
<&cru PCLK_RGA_PRE>;
pm_qos = <&qos_ebc>,
<&qos_iep>,
<&qos_jpeg_dec>,
<&qos_jpeg_enc>,
<&qos_rga_rd>,
<&qos_rga_wr>;
};
pd_vpu@RK3568_PD_VPU {
reg = <RK3568_PD_VPU>;
clocks = <&cru HCLK_VPU_PRE>;
pm_qos = <&qos_vpu>;
};
pd_rkvdec@RK3568_PD_RKVDEC {
clocks = <&cru HCLK_RKVDEC_PRE>;
reg = <RK3568_PD_RKVDEC>;
pm_qos = <&qos_rkvdec>;
};
pd_rkvenc@RK3568_PD_RKVENC {
reg = <RK3568_PD_RKVENC>;
clocks = <&cru HCLK_RKVENC_PRE>;
pm_qos = <&qos_rkvenc_rd_m0>,
<&qos_rkvenc_rd_m1>,
<&qos_rkvenc_wr_m0>;
};
pd_pipe@RK3568_PD_PIPE {
reg = <RK3568_PD_PIPE>;
clocks = <&cru PCLK_PIPE>;
pm_qos = <&qos_pcie2x1>,
<&qos_pcie3x1>,
<&qos_pcie3x2>,
<&qos_sata0>,
<&qos_sata1>,
<&qos_sata2>,
<&qos_usb3_0>,
<&qos_usb3_1>;
};
};
};
pvtm@fde00000 {
compatible = "rockchip,rk3568-core-pvtm";
reg = <0x0 0xfde00000 0x0 0x100>;
#address-cells = <1>;
#size-cells = <0>;
pvtm@0 {
reg = <0>;
clocks = <&cru CLK_CORE_PVTM>, <&cru PCLK_CORE_PVTM>;
clock-names = "clk", "pclk";
resets = <&cru SRST_CORE_PVTM>, <&cru SRST_P_CORE_PVTM>;
reset-names = "rts", "rst-p";
thermal-zone = "soc-thermal";
};
};
rknpu: npu@fde40000 {
compatible = "rockchip,rk3568-rknpu", "rockchip,rknpu";
reg = <0x0 0xfde40000 0x0 0x10000>;
interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&scmi_clk 2>, <&cru CLK_NPU>, <&cru ACLK_NPU>, <&cru HCLK_NPU>;
clock-names = "scmi_clk", "clk", "aclk", "hclk";
assigned-clocks = <&cru CLK_NPU>;
assigned-clock-rates = <600000000>;
resets = <&cru SRST_A_NPU>, <&cru SRST_H_NPU>;
reset-names = "srst_a", "srst_h";
power-domains = <&power RK3568_PD_NPU>;
operating-points-v2 = <&npu_opp_table>;
iommus = <&rknpu_mmu>;
status = "disabled";
};
npu_opp_table: npu-opp-table {
compatible = "operating-points-v2";
mbist-vmin = <825000 900000 950000>;
nvmem-cells = <&npu_leakage>, <&core_pvtm>, <&mbist_vmin>;
nvmem-cell-names = "leakage", "pvtm", "mbist-vmin";
rockchip,temp-hysteresis = <5000>;
rockchip,low-temp = <0>;
rockchip,low-temp-adjust-volt = <
/* MHz MHz uV */
0 700 50000
>;
rockchip,pvtm-voltage-sel = <
0 84000 0
84001 91000 1
91001 100000 2
>;
rockchip,pvtm-ch = <0 5>;
opp-200000000 {
opp-hz = /bits/ 64 <200000000>;
opp-microvolt = <850000 850000 1000000>;
opp-microvolt-L0 = <850000 850000 1000000>;
opp-microvolt-L1 = <825000 825000 1000000>;
opp-microvolt-L2 = <825000 825000 1000000>;
};
opp-300000000 {
opp-hz = /bits/ 64 <297000000>;
opp-microvolt = <850000 850000 1000000>;
opp-microvolt-L0 = <850000 850000 1000000>;
opp-microvolt-L1 = <825000 825000 1000000>;
opp-microvolt-L2 = <825000 825000 1000000>;
};
opp-400000000 {
opp-hz = /bits/ 64 <400000000>;
opp-microvolt = <850000 850000 1000000>;
opp-microvolt-L0 = <850000 850000 1000000>;
opp-microvolt-L1 = <825000 825000 1000000>;
opp-microvolt-L2 = <825000 825000 1000000>;
};
opp-600000000 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <875000 875000 1000000>;
opp-microvolt-L0 = <875000 875000 1000000>;
opp-microvolt-L1 = <825000 825000 1000000>;
opp-microvolt-L2 = <825000 825000 1000000>;
};
opp-700000000 {
opp-hz = /bits/ 64 <700000000>;
opp-microvolt = <900000 900000 1000000>;
opp-microvolt-L0 = <900000 900000 1000000>;
opp-microvolt-L1 = <850000 850000 1000000>;
opp-microvolt-L2 = <850000 850000 1000000>;
};
opp-800000000 {
opp-hz = /bits/ 64 <800000000>;
opp-microvolt = <925000 925000 1000000>;
opp-microvolt-L0 = <925000 925000 1000000>;
opp-microvolt-L1 = <875000 875000 1000000>;
opp-microvolt-L2 = <875000 875000 1000000>;
};
opp-900000000 {
opp-hz = /bits/ 64 <900000000>;
opp-microvolt = <975000 975000 1000000>;
opp-microvolt-L0 = <975000 975000 1000000>;
opp-microvolt-L1 = <925000 925000 1000000>;
opp-microvolt-L2 = <900000 900000 1000000>;
};
opp-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <1000000 1000000 1000000>;
opp-microvolt-L0 = <1000000 1000000 1000000>;
opp-microvolt-L1 = <950000 950000 1000000>;
opp-microvolt-L2 = <925000 925000 1000000>;
status = "disabled";
};
};
bus_npu: bus-npu {
compatible = "rockchip,rk3568-bus";
rockchip,busfreq-policy = "clkfreq";
clocks = <&scmi_clk 2>;
clock-names = "bus";
operating-points-v2 = <&bus_npu_opp_table>;
status = "disabled";
};
bus_npu_opp_table: bus-npu-opp-table {
compatible = "operating-points-v2";
opp-shared;
nvmem-cells = <&core_pvtm>;
nvmem-cell-names = "pvtm";
rockchip,pvtm-voltage-sel = <
0 84000 0
84001 91000 1
91001 100000 2
>;
rockchip,pvtm-ch = <0 5>;
opp-700000000 {
opp-hz = /bits/ 64 <700000000>;
opp-microvolt = <0>;
};
opp-900000000 {
opp-hz = /bits/ 64 <900000000>;
opp-microvolt = <900000>;
};
opp-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <950000>;
opp-microvolt-L0 = <950000>;
opp-microvolt-L1 = <925000>;
opp-microvolt-L2 = <0>;
};
};
rknpu_mmu: iommu@fde4b000 {
compatible = "rockchip,iommu-v2";
reg = <0x0 0xfde4b000 0x0 0x40>;
interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "rknpu_mmu";
clocks = <&cru ACLK_NPU>, <&cru HCLK_NPU>;
clock-names = "aclk", "iface";
power-domains = <&power RK3568_PD_NPU>;
#iommu-cells = <0>;
status = "disabled";
};
gpu: gpu@fde60000 {
compatible = "arm,mali-bifrost";
reg = <0x0 0xfde60000 0x0 0x4000>;
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "GPU", "MMU", "JOB";
upthreshold = <40>;
downdifferential = <10>;
clocks = <&scmi_clk 1>, <&cru CLK_GPU>;
clock-names = "clk_mali", "clk_gpu";
power-domains = <&power RK3568_PD_GPU>;
#cooling-cells = <2>;
operating-points-v2 = <&gpu_opp_table>;
status = "disabled";
gpu_power_model: power-model {
compatible = "simple-power-model";
leakage-range= <5 15>;
ls = <(-24002) 22823 0>;
static-coefficient = <100000>;
dynamic-coefficient = <953>;
ts = <(-108890) 63610 (-1355) 20>;
thermal-zone = "gpu-thermal";
};
};
gpu_opp_table: opp-table2 {
compatible = "operating-points-v2";
mbist-vmin = <825000 900000 950000>;
nvmem-cells = <&gpu_leakage>, <&core_pvtm>, <&mbist_vmin>;
nvmem-cell-names = "leakage", "pvtm", "mbist-vmin";
rockchip,pvtm-voltage-sel = <
0 84000 0
84001 91000 1
91001 100000 2
>;
rockchip,pvtm-ch = <0 5>;
opp-200000000 {
opp-hz = /bits/ 64 <200000000>;
opp-microvolt = <850000>;
opp-microvolt-L0 = <850000>;
opp-microvolt-L1 = <825000>;
opp-microvolt-L2 = <825000>;
};
opp-300000000 {
opp-hz = /bits/ 64 <300000000>;
opp-microvolt = <850000>;
opp-microvolt-L0 = <850000>;
opp-microvolt-L1 = <825000>;
opp-microvolt-L2 = <825000>;
};
opp-400000000 {
opp-hz = /bits/ 64 <400000000>;
opp-microvolt = <850000>;
opp-microvolt-L0 = <850000>;
opp-microvolt-L1 = <825000>;
opp-microvolt-L2 = <825000>;
};
opp-600000000 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <875000>;
opp-microvolt-L0 = <875000>;
opp-microvolt-L1 = <825000>;
opp-microvolt-L2 = <825000>;
};
opp-700000000 {
opp-hz = /bits/ 64 <700000000>;
opp-microvolt = <950000>;
opp-microvolt-L0 = <950000>;
opp-microvolt-L1 = <900000>;
opp-microvolt-L2 = <850000>;
};
opp-800000000 {
opp-hz = /bits/ 64 <800000000>;
opp-microvolt = <1000000>;
opp-microvolt-L0 = <1000000>;
opp-microvolt-L1 = <950000>;
opp-microvolt-L2 = <900000>;
};
};
pvtm@fde80000 {
compatible = "rockchip,rk3568-gpu-pvtm";
reg = <0x0 0xfde80000 0x0 0x100>;
#address-cells = <1>;
#size-cells = <0>;
pvtm@1 {
reg = <1>;
clocks = <&cru CLK_GPU_PVTM>, <&cru PCLK_GPU_PVTM>;
clock-names = "clk", "pclk";
resets = <&cru SRST_GPU_PVTM>, <&cru SRST_P_GPU_PVTM>;
reset-names = "rts", "rst-p";
thermal-zone = "gpu-thermal";
};
};
pvtm@fde90000 {
compatible = "rockchip,rk3568-npu-pvtm";
reg = <0x0 0xfde90000 0x0 0x100>;
#address-cells = <1>;
#size-cells = <0>;
pvtm@2 {
reg = <2>;
clocks = <&cru CLK_NPU_PVTM>, <&cru PCLK_NPU_PVTM>,
<&cru HCLK_NPU_PRE>;
clock-names = "clk", "pclk", "hclk";
resets = <&cru SRST_NPU_PVTM>, <&cru SRST_P_NPU_PVTM>;
reset-names = "rts", "rst-p";
thermal-zone = "soc-thermal";
};
};
vdpu: vdpu@fdea0400 {
compatible = "rockchip,vpu-decoder-v2";
reg = <0x0 0xfdea0400 0x0 0x400>;
interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "irq_dec";
clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
clock-names = "aclk_vcodec", "hclk_vcodec";
resets = <&cru SRST_A_VPU>, <&cru SRST_H_VPU>;
reset-names = "video_a", "video_h";
iommus = <&vdpu_mmu>;
power-domains = <&power RK3568_PD_VPU>;
rockchip,srv = <&mpp_srv>;
rockchip,taskqueue-node = <0>;
rockchip,resetgroup-node = <0>;
status = "disabled";
};
vdpu_mmu: iommu@fdea0800 {
compatible = "rockchip,iommu-v2";
reg = <0x0 0xfdea0800 0x0 0x40>;
interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vdpu_mmu";
clock-names = "aclk", "iface";
clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
power-domains = <&power RK3568_PD_VPU>;
#iommu-cells = <0>;
status = "disabled";
};
rk_rga: rk_rga@fdeb0000 {
compatible = "rockchip,rga2";
reg = <0x0 0xfdeb0000 0x0 0x1000>;
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru CLK_RGA_CORE>;
clock-names = "aclk_rga", "hclk_rga", "clk_rga";
power-domains = <&power RK3568_PD_RGA>;
status = "disabled";
};
ebc: ebc@fdec0000 {
compatible = "rockchip,rk3568-ebc-tcon";
reg = <0x0 0xfdec0000 0x0 0x5000>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_EBC>, <&cru DCLK_EBC>;
clock-names = "hclk", "dclk";
power-domains = <&power RK3568_PD_RGA>;
rockchip,grf = <&grf>;
pinctrl-names = "default";
pinctrl-0 = <&ebc_pins>;
status = "disabled";
};
jpegd: jpegd@fded0000 {
compatible = "rockchip,rkv-jpeg-decoder-v1";
reg = <0x0 0xfded0000 0x0 0x400>;
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_JDEC>, <&cru HCLK_JDEC>;
clock-names = "aclk_vcodec", "hclk_vcodec";
rockchip,disable-auto-freq;
resets = <&cru SRST_A_JDEC>, <&cru SRST_H_JDEC>;
reset-names = "video_a", "video_h";
iommus = <&jpegd_mmu>;
rockchip,srv = <&mpp_srv>;
rockchip,taskqueue-node = <1>;
rockchip,resetgroup-node = <1>;
power-domains = <&power RK3568_PD_RGA>;
status = "disabled";
};
jpegd_mmu: iommu@fded0480 {
compatible = "rockchip,iommu-v2";
reg = <0x0 0xfded0480 0x0 0x40>;
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "jpegd_mmu";
clock-names = "aclk", "iface";
clocks = <&cru ACLK_JDEC>, <&cru HCLK_JDEC>;
power-domains = <&power RK3568_PD_RGA>;
#iommu-cells = <0>;
status = "disabled";
};
vepu: vepu@fdee0000 {
compatible = "rockchip,vpu-encoder-v2";
reg = <0x0 0xfdee0000 0x0 0x400>;
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>;
clock-names = "aclk_vcodec", "hclk_vcodec";
rockchip,disable-auto-freq;
resets = <&cru SRST_A_JENC>, <&cru SRST_H_JENC>;
reset-names = "video_a", "video_h";
iommus = <&vepu_mmu>;
rockchip,srv = <&mpp_srv>;
rockchip,taskqueue-node = <2>;
rockchip,resetgroup-node = <2>;
power-domains = <&power RK3568_PD_RGA>;
status = "disabled";
};
vepu_mmu: iommu@fdee0800 {
compatible = "rockchip,iommu-v2";
reg = <0x0 0xfdee0800 0x0 0x40>;
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vepu_mmu";
clock-names = "aclk", "iface";
clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>;
power-domains = <&power RK3568_PD_RGA>;
#iommu-cells = <0>;
status = "disabled";
};
iep: iep@fdef0000 {
compatible = "rockchip,iep-v2";
reg = <0x0 0xfdef0000 0x0 0x500>;
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>, <&cru CLK_IEP_CORE>;
clock-names = "aclk", "hclk", "sclk";
resets = <&cru SRST_A_IEP>, <&cru SRST_H_IEP>,
<&cru SRST_IEP_CORE>;
reset-names = "rst_a", "rst_h", "rst_s";
power-domains = <&power RK3568_PD_RGA>;
rockchip,srv = <&mpp_srv>;
rockchip,taskqueue-node = <5>;
rockchip,resetgroup-node = <5>;
iommus = <&iep_mmu>;
status = "disabled";
};
iep_mmu: iommu@fdef0800 {
compatible = "rockchip,iommu-v2";
reg = <0x0 0xfdef0800 0x0 0x100>;
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "iep_mmu";
clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
clock-names = "aclk", "iface";
#iommu-cells = <0>;
power-domains = <&power RK3568_PD_RGA>;
//rockchip,disable-device-link-resume;
status = "disabled";
};
eink: eink@fdf00000 {
compatible = "rockchip,rk3568-eink-tcon";
reg = <0x0 0xfdf00000 0x0 0x74>;
interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_EINK>, <&cru HCLK_EINK>;
clock-names = "pclk", "hclk";
status = "disabled";
};
rkvenc: rkvenc@fdf40000 {
compatible = "rockchip,rkv-encoder-v1";
reg = <0x0 0xfdf40000 0x0 0x400>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "irq_enc";
clocks = <&cru ACLK_RKVENC>, <&cru HCLK_RKVENC>,
<&cru CLK_RKVENC_CORE>;
clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core";
rockchip,normal-rates = <297000000>, <0>, <297000000>;
resets = <&cru SRST_A_RKVENC>, <&cru SRST_H_RKVENC>,
<&cru SRST_RKVENC_CORE>;
reset-names = "video_a", "video_h", "video_core";
assigned-clocks = <&cru ACLK_RKVENC>, <&cru CLK_RKVENC_CORE>;
assigned-clock-rates = <297000000>, <297000000>;
iommus = <&rkvenc_mmu>;
node-name = "rkvenc";
rockchip,srv = <&mpp_srv>;
rockchip,taskqueue-node = <3>;
rockchip,resetgroup-node = <3>;
power-domains = <&power RK3568_PD_RKVENC>;
operating-points-v2 = <&rkvenc_opp_table>;
status = "disabled";
};
rkvenc_opp_table: rkvenc-opp-table {
compatible = "operating-points-v2";
nvmem-cells = <&core_pvtm>;
nvmem-cell-names = "pvtm";
rockchip,pvtm-voltage-sel = <
0 84000 0
84001 91000 1
91001 100000 2
>;
rockchip,pvtm-ch = <0 5>;
opp-297000000 {
opp-hz = /bits/ 64 <297000000>;
opp-microvolt = <0>;
};
opp-400000000 {
opp-hz = /bits/ 64 <400000000>;
opp-microvolt = <950000>;
opp-microvolt-L0 = <950000>;
opp-microvolt-L1 = <925000>;
opp-microvolt-L2 = <0>;
};
};
rkvenc_mmu: iommu@fdf40f00 {
compatible = "rockchip,iommu-v2";
reg = <0x0 0xfdf40f00 0x0 0x40>, <0x0 0xfdf40f40 0x0 0x40>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "rkvenc_mmu0", "rkvenc_mmu1";
clocks = <&cru ACLK_RKVENC>, <&cru HCLK_RKVENC>;
clock-names = "aclk", "iface";
rockchip,disable-mmu-reset;
rockchip,enable-cmd-retry;
#iommu-cells = <0>;
power-domains = <&power RK3568_PD_RKVENC>;
status = "disabled";
};
rkvdec: rkvdec@fdf80200 {
compatible = "rockchip,rkv-decoder-rk3568", "rockchip,rkv-decoder-v2";
reg = <0x0 0xfdf80200 0x0 0x400>, <0x0 0xfdf80100 0x0 0x100>;
reg-names = "regs", "link";
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "irq_dec";
clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>,
<&cru CLK_RKVDEC_CA>, <&cru CLK_RKVDEC_CORE>,
<&cru CLK_RKVDEC_HEVC_CA>;
clock-names = "aclk_vcodec", "hclk_vcodec","clk_cabac",
"clk_core", "clk_hevc_cabac";
rockchip,normal-rates = <297000000>, <0>, <297000000>,
<297000000>, <600000000>;
rockchip,advanced-rates = <396000000>, <0>, <396000000>,
<396000000>, <600000000>;
rockchip,default-max-load = <2088960>;
resets = <&cru SRST_A_RKVDEC>, <&cru SRST_H_RKVDEC>,
<&cru SRST_RKVDEC_CA>, <&cru SRST_RKVDEC_CORE>,
<&cru SRST_RKVDEC_HEVC_CA>;
assigned-clocks = <&cru ACLK_RKVDEC>, <&cru CLK_RKVDEC_CA>,
<&cru CLK_RKVDEC_CORE>, <&cru CLK_RKVDEC_HEVC_CA>;
assigned-clock-rates = <297000000>, <297000000>, <297000000>, <297000000>;
reset-names = "video_a", "video_h", "video_cabac",
"video_core", "video_hevc_cabac";
power-domains = <&power RK3568_PD_RKVDEC>;
iommus = <&rkvdec_mmu>;
rockchip,srv = <&mpp_srv>;
rockchip,taskqueue-node = <4>;
rockchip,resetgroup-node = <4>;
rockchip,sram = <&rkvdec_sram>;
/* rcb_iova: start and size */
rockchip,rcb-iova = <0x10000000 65536>;
rockchip,rcb-min-width = <512>;
rockchip,task-capacity = <16>;
status = "disabled";
};
rkvdec_mmu: iommu@fdf80800 {
compatible = "rockchip,iommu-v2";
reg = <0x0 0xfdf80800 0x0 0x40>, <0x0 0xfdf80840 0x0 0x40>;
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "rkvdec_mmu";
clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
clock-names = "aclk", "iface";
power-domains = <&power RK3568_PD_RKVDEC>;
#iommu-cells = <0>;
status = "disabled";
};
mipi_csi2: mipi-csi2@fdfb0000 {
compatible = "rockchip,rk3568-mipi-csi2";
reg = <0x0 0xfdfb0000 0x0 0x10000>;
reg-names = "csihost_regs";
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "csi-intr1", "csi-intr2";
clocks = <&cru PCLK_CSI2HOST1>;
clock-names = "pclk_csi2host";
resets = <&cru SRST_P_CSI2HOST1>;
reset-names = "srst_csihost_p";
status = "disabled";
};
rkcif: rkcif@fdfe0000 {
compatible = "rockchip,rk3568-cif";
reg = <0x0 0xfdfe0000 0x0 0x8000>;
reg-names = "cif_regs";
interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "cif-intr";
clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>,
<&cru DCLK_VICAP>, <&cru ICLK_VICAP_G>;
clock-names = "aclk_cif", "hclk_cif",
"dclk_cif", "iclk_cif_g";
resets = <&cru SRST_A_VICAP>, <&cru SRST_H_VICAP>,
<&cru SRST_D_VICAP>, <&cru SRST_P_VICAP>,
<&cru SRST_I_VICAP>;
reset-names = "rst_cif_a", "rst_cif_h",
"rst_cif_d", "rst_cif_p",
"rst_cif_i";
assigned-clocks = <&cru DCLK_VICAP>;
assigned-clock-rates = <300000000>;
power-domains = <&power RK3568_PD_VI>;
rockchip,grf = <&grf>;
iommus = <&rkcif_mmu>;
status = "disabled";
};
rkcif_mmu: iommu@fdfe0800 {
compatible = "rockchip,iommu-v2";
reg = <0x0 0xfdfe0800 0x0 0x100>;
interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "cif_mmu";
clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>;
clock-names = "aclk", "iface";
power-domains = <&power RK3568_PD_VI>;
rockchip,disable-mmu-reset;
#iommu-cells = <0>;
status = "disabled";
};
rkcif_dvp: rkcif_dvp {
compatible = "rockchip,rkcif-dvp";
rockchip,hw = <&rkcif>;
status = "disabled";
};
rkcif_dvp_sditf: rkcif_dvp_sditf {
compatible = "rockchip,rkcif-sditf";
rockchip,cif = <&rkcif_dvp>;
status = "disabled";
};
rkcif_mipi_lvds: rkcif_mipi_lvds {
compatible = "rockchip,rkcif-mipi-lvds";
rockchip,hw = <&rkcif>;
status = "disabled";
};
rkcif_mipi_lvds_sditf: rkcif_mipi_lvds_sditf {
compatible = "rockchip,rkcif-sditf";
rockchip,cif = <&rkcif_mipi_lvds>;
status = "disabled";
};
rkisp: rkisp@fdff0000 {
compatible = "rockchip,rk3568-rkisp";
reg = <0x0 0xfdff0000 0x0 0x10000>;
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "mipi_irq", "mi_irq", "isp_irq";
clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>, <&cru CLK_ISP>;
clock-names = "aclk_isp", "hclk_isp", "clk_isp";
resets = <&cru SRST_ISP>, <&cru SRST_H_ISP>;
reset-names = "isp", "isp-h";
rockchip,grf = <&grf>;
power-domains = <&power RK3568_PD_VI>;
iommus = <&rkisp_mmu>;
rockchip,iq-feature = /bits/ 64 <0x3FBFFFE67FF>;
status = "disabled";
};
rkisp_mmu: iommu@fdff1a00 {
compatible = "rockchip,iommu-v2";
reg = <0x0 0xfdff1a00 0x0 0x100>;
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "isp_mmu";
clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
clock-names = "aclk", "iface";
power-domains = <&power RK3568_PD_VI>;
#iommu-cells = <0>;
rockchip,disable-mmu-reset;
status = "disabled";
};
rkisp_vir0: rkisp-vir0 {
compatible = "rockchip,rkisp-vir";
rockchip,hw = <&rkisp>;
status = "disabled";
};
rkisp_vir1: rkisp-vir1 {
compatible = "rockchip,rkisp-vir";
rockchip,hw = <&rkisp>;
status = "disabled";
};
gmac1: ethernet@fe010000 {
compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";
reg = <0x0 0xfe010000 0x0 0x10000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq", "eth_wake_irq";
rockchip,grf = <&grf>;
clocks = <&cru SCLK_GMAC1>, <&cru SCLK_GMAC1_RX_TX>,
<&cru SCLK_GMAC1_RX_TX>, <&cru CLK_MAC1_REFOUT>,
<&cru ACLK_GMAC1>, <&cru PCLK_GMAC1>,
<&cru SCLK_GMAC1_RX_TX>, <&cru CLK_GMAC1_PTP_REF>,
<&cru PCLK_XPCS>;
clock-names = "stmmaceth", "mac_clk_rx",
"mac_clk_tx", "clk_mac_refout",
"aclk_mac", "pclk_mac",
"clk_mac_speed", "ptp_ref",
"pclk_xpcs";
resets = <&cru SRST_A_GMAC1>;
reset-names = "stmmaceth";
snps,mixed-burst;
snps,tso;
snps,axi-config = <&gmac1_stmmac_axi_setup>;
snps,mtl-rx-config = <&gmac1_mtl_rx_setup>;
snps,mtl-tx-config = <&gmac1_mtl_tx_setup>;
status = "disabled";
mdio1: mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <0x1>;
#size-cells = <0x0>;
};
gmac1_stmmac_axi_setup: stmmac-axi-config {
snps,wr_osr_lmt = <4>;
snps,rd_osr_lmt = <8>;
snps,blen = <0 0 0 0 16 8 4>;
};
gmac1_mtl_rx_setup: rx-queues-config {
snps,rx-queues-to-use = <1>;
queue0 {};
};
gmac1_mtl_tx_setup: tx-queues-config {
snps,tx-queues-to-use = <1>;
queue0 {};
};
};
vop: vop@fe040000 {
compatible = "rockchip,rk3568-vop";
reg = <0x0 0xfe040000 0x0 0x3000>, <0x0 0xfe044000 0x0 0x1000>;
reg-names = "regs", "gamma_lut";
rockchip,grf = <&grf>;
interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>, <&cru DCLK_VOP0>, <&cru DCLK_VOP1>, <&cru DCLK_VOP2>;
clock-names = "aclk_vop", "hclk_vop", "dclk_vp0", "dclk_vp1", "dclk_vp2";
iommus = <&vop_mmu>;
power-domains = <&power RK3568_PD_VO>;
status = "disabled";
vop_out: ports {
#address-cells = <1>;
#size-cells = <0>;
vp0: port@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
vp0_out_dsi0: endpoint@0 {
reg = <0>;
remote-endpoint = <&dsi0_in_vp0>;
};
vp0_out_dsi1: endpoint@1 {
reg = <1>;
remote-endpoint = <&dsi1_in_vp0>;
};
vp0_out_edp: endpoint@2 {
reg = <2>;
remote-endpoint = <&edp_in_vp0>;
};
vp0_out_hdmi: endpoint@3 {
reg = <3>;
remote-endpoint = <&hdmi_in_vp0>;
};
};
vp1: port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
vp1_out_dsi0: endpoint@0 {
reg = <0>;
remote-endpoint = <&dsi0_in_vp1>;
};
vp1_out_dsi1: endpoint@1 {
reg = <1>;
remote-endpoint = <&dsi1_in_vp1>;
};
vp1_out_edp: endpoint@2 {
reg = <2>;
remote-endpoint = <&edp_in_vp1>;
};
vp1_out_hdmi: endpoint@3 {
reg = <3>;
remote-endpoint = <&hdmi_in_vp1>;
};
vp1_out_lvds: endpoint@4 {
reg = <4>;
remote-endpoint = <&lvds_in_vp1>;
};
};
vp2: port@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
vp2_out_lvds: endpoint@0 {
reg = <0>;
remote-endpoint = <&lvds_in_vp2>;
};
vp2_out_rgb: endpoint@1 {
reg = <1>;
remote-endpoint = <&rgb_in_vp2>;
};
};
};
};
vop_mmu: iommu@fe043e00 {
compatible = "rockchip,iommu-v2";
reg = <0x0 0xfe043e00 0x0 0x100>, <0x0 0xfe043f00 0x0 0x100>;
interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vop_mmu";
clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
clock-names = "aclk", "iface";
#iommu-cells = <0>;
status = "disabled";
};
dsi0: dsi@fe060000 {
compatible = "rockchip,rk3568-mipi-dsi";
reg = <0x0 0xfe060000 0x0 0x10000>;
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_DSITX_0>, <&cru HCLK_VO>, <&video_phy0>;
clock-names = "pclk", "hclk", "hs_clk";
resets = <&cru SRST_P_DSITX_0>;
reset-names = "apb";
phys = <&video_phy0>;
phy-names = "mipi_dphy";
power-domains = <&power RK3568_PD_VO>;
rockchip,grf = <&grf>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
dsi0_in: port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
dsi0_in_vp0: endpoint@0 {
reg = <0>;
remote-endpoint = <&vp0_out_dsi0>;
status = "disabled";
};
dsi0_in_vp1: endpoint@1 {
reg = <1>;
remote-endpoint = <&vp1_out_dsi0>;
status = "disabled";
};
};
};
};
dsi1: dsi@fe070000 {
compatible = "rockchip,rk3568-mipi-dsi";
reg = <0x0 0xfe070000 0x0 0x10000>;
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_DSITX_1>, <&cru HCLK_VO>, <&video_phy1>;
clock-names = "pclk", "hclk", "hs_clk";
resets = <&cru SRST_P_DSITX_1>;
reset-names = "apb";
phys = <&video_phy1>;
phy-names = "mipi_dphy";
power-domains = <&power RK3568_PD_VO>;
rockchip,grf = <&grf>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
dsi1_in: port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
dsi1_in_vp0: endpoint@0 {
reg = <0>;
remote-endpoint = <&vp0_out_dsi1>;
status = "disabled";
};
dsi1_in_vp1: endpoint@1 {
reg = <1>;
remote-endpoint = <&vp1_out_dsi1>;
status = "disabled";
};
};
};
};
hdmi: hdmi@fe0a0000 {
compatible = "rockchip,rk3568-dw-hdmi";
reg = <0x0 0xfe0a0000 0x0 0x20000>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_HDMI_HOST>,
<&cru CLK_HDMI_SFR>,
<&cru CLK_HDMI_CEC>,
<&pmucru PLL_HPLL>,
<&cru HCLK_VOP>;
clock-names = "iahb", "isfr", "cec", "ref", "hclk";
power-domains = <&power RK3568_PD_VO>;
reg-io-width = <4>;
rockchip,grf = <&grf>;
#sound-dai-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&hdmitx_scl &hdmitx_sda &hdmitxm0_cec>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
hdmi_in: port {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
hdmi_in_vp0: endpoint@0 {
reg = <0>;
remote-endpoint = <&vp0_out_hdmi>;
status = "disabled";
};
hdmi_in_vp1: endpoint@1 {
reg = <1>;
remote-endpoint = <&vp1_out_hdmi>;
status = "disabled";
};
};
};
};
edp: edp@fe0c0000 {
compatible = "rockchip,rk3568-edp";
reg = <0x0 0xfe0c0000 0x0 0x10000>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pmucru XIN_OSC0_EDPPHY_G>, <&cru PCLK_EDP_CTRL>,
<&cru CLK_EDP_200M>, <&cru HCLK_VO>;
clock-names = "dp", "pclk", "spdif", "hclk";
resets = <&cru SRST_EDP_24M>, <&cru SRST_P_EDP_CTRL>;
reset-names = "dp", "apb";
phys = <&edp_phy>;
phy-names = "dp";
power-domains = <&power RK3568_PD_VO>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
edp_in: port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
edp_in_vp0: endpoint@0 {
reg = <0>;
remote-endpoint = <&vp0_out_edp>;
status = "disabled";
};
edp_in_vp1: endpoint@1 {
reg = <1>;
remote-endpoint = <&vp1_out_edp>;
status = "disabled";
};
};
};
};
nocp_cpu: nocp-cpu@fe102000 {
compatible = "rockchip,rk3568-nocp";
reg = <0x0 0xfe102000 0x0 0x400>;
};
nocp_gpu_vpu_rga_venc: nocp-gpu-vpu-rga-venc@fe102400 {
compatible = "rockchip,rk3568-nocp";
reg = <0x0 0xfe102400 0x0 0x400>;
};
nocp_npu_vdec: nocp-vdec@fe102800 {
compatible = "rockchip,rk3568-nocp";
reg = <0x0 0xfe102800 0x0 0x400>;
};
nocp_vi_usb_peri_pipe: nocp-vi-usb-peri-pipe@fe102c00 {
compatible = "rockchip,rk3568-nocp";
reg = <0x0 0xfe102c00 0x0 0x400>;
};
nocp_vo: nocp-vo@fe103000 {
compatible = "rockchip,rk3568-nocp";
reg = <0x0 0xfe103000 0x0 0x400>;
};
qos_gpu: qos@fe128000 {
compatible = "syscon";
reg = <0x0 0xfe128000 0x0 0x20>;
};
qos_rkvenc_rd_m0: qos@fe138080 {
compatible = "syscon";
reg = <0x0 0xfe138080 0x0 0x20>;
};
qos_rkvenc_rd_m1: qos@fe138100 {
compatible = "syscon";
reg = <0x0 0xfe138100 0x0 0x20>;
};
qos_rkvenc_wr_m0: qos@fe138180 {
compatible = "syscon";
reg = <0x0 0xfe138180 0x0 0x20>;
};
qos_isp: qos@fe148000 {
compatible = "syscon";
reg = <0x0 0xfe148000 0x0 0x20>;
};
qos_vicap0: qos@fe148080 {
compatible = "syscon";
reg = <0x0 0xfe148080 0x0 0x20>;
};
qos_vicap1: qos@fe148100 {
compatible = "syscon";
reg = <0x0 0xfe148100 0x0 0x20>;
};
qos_vpu: qos@fe150000 {
compatible = "syscon";
reg = <0x0 0xfe150000 0x0 0x20>;
};
qos_ebc: qos@fe158000 {
compatible = "syscon";
reg = <0x0 0xfe158000 0x0 0x20>;
};
qos_iep: qos@fe158100 {
compatible = "syscon";
reg = <0x0 0xfe158100 0x0 0x20>;
};
qos_jpeg_dec: qos@fe158180 {
compatible = "syscon";
reg = <0x0 0xfe158180 0x0 0x20>;
};
qos_jpeg_enc: qos@fe158200 {
compatible = "syscon";
reg = <0x0 0xfe158200 0x0 0x20>;
};
qos_rga_rd: qos@fe158280 {
compatible = "syscon";
reg = <0x0 0xfe158280 0x0 0x20>;
};
qos_rga_wr: qos@fe158300 {
compatible = "syscon";
reg = <0x0 0xfe158300 0x0 0x20>;
};
qos_npu: qos@fe180000 {
compatible = "syscon";
reg = <0x0 0xfe180000 0x0 0x20>;
};
qos_pcie2x1: qos@fe190000 {
compatible = "syscon";
reg = <0x0 0xfe190000 0x0 0x20>;
};
qos_pcie3x1: qos@fe190080 {
compatible = "syscon";
reg = <0x0 0xfe190080 0x0 0x20>;
};
qos_pcie3x2: qos@fe190100 {
compatible = "syscon";
reg = <0x0 0xfe190100 0x0 0x20>;
};
qos_sata0: qos@fe190200 {
compatible = "syscon";
reg = <0x0 0xfe190200 0x0 0x20>;
};
qos_sata1: qos@fe190280 {
compatible = "syscon";
reg = <0x0 0xfe190280 0x0 0x20>;
};
qos_sata2: qos@fe190300 {
compatible = "syscon";
reg = <0x0 0xfe190300 0x0 0x20>;
};
qos_usb3_0: qos@fe190380 {
compatible = "syscon";
reg = <0x0 0xfe190380 0x0 0x20>;
};
qos_usb3_1: qos@fe190400 {
compatible = "syscon";
reg = <0x0 0xfe190400 0x0 0x20>;
};
qos_rkvdec: qos@fe198000 {
compatible = "syscon";
reg = <0x0 0xfe198000 0x0 0x20>;
};
qos_hdcp: qos@fe1a8000 {
compatible = "syscon";
reg = <0x0 0xfe1a8000 0x0 0x20>;
};
qos_vop_m0: qos@fe1a8080 {
compatible = "syscon";
reg = <0x0 0xfe1a8080 0x0 0x20>;
};
qos_vop_m1: qos@fe1a8100 {
compatible = "syscon";
reg = <0x0 0xfe1a8100 0x0 0x20>;
};
sdmmc2: dwmmc@fe000000 {
compatible = "rockchip,rk3568-dw-mshc",
"rockchip,rk3288-dw-mshc";
reg = <0x0 0xfe000000 0x0 0x4000>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
max-frequency = <150000000>;
clocks = <&cru HCLK_SDMMC2>, <&cru CLK_SDMMC2>,
<&cru SCLK_SDMMC2_DRV>, <&cru SCLK_SDMMC2_SAMPLE>;
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
resets = <&cru SRST_SDMMC2>;
reset-names = "reset";
status = "disabled";
};
dfi: dfi@fe230000 {
reg = <0x00 0xfe230000 0x00 0x400>;
compatible = "rockchip,rk3568-dfi";
rockchip,pmugrf = <&pmugrf>;
status = "disabled";
};
dmc: dmc {
compatible = "rockchip,rk3568-dmc";
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "complete";
devfreq-events = <&dfi>, <&nocp_cpu>;
clocks = <&scmi_clk 3>;
clock-names = "dmc_clk";
operating-points-v2 = <&dmc_opp_table>;
vop-bw-dmc-freq = <
/* min_bw(MB/s) max_bw(MB/s) freq(KHz) */
0 286 324000
287 99999 528000
>;
vop-frame-bw-dmc-freq = <
/* min_bw(MB/s) max_bw(MB/s) freq(KHz) */
0 620 324000
621 99999 780000
>;
cpu-bw-dmc-freq = <
/* min_bw(MB/s) max_bw(MB/s) freq(KHz) */
0 350 324000
351 400 528000
401 99999 780000
>;
upthreshold = <40>;
downdifferential = <20>;
system-status-level = <
/*system status freq level*/
SYS_STATUS_NORMAL DMC_FREQ_LEVEL_MID_HIGH
SYS_STATUS_REBOOT DMC_FREQ_LEVEL_HIGH
SYS_STATUS_SUSPEND DMC_FREQ_LEVEL_LOW
SYS_STATUS_VIDEO_4K DMC_FREQ_LEVEL_MID_HIGH
SYS_STATUS_VIDEO_4K_10B DMC_FREQ_LEVEL_MID_HIGH
SYS_STATUS_BOOST DMC_FREQ_LEVEL_HIGH
SYS_STATUS_ISP DMC_FREQ_LEVEL_HIGH
SYS_STATUS_PERFORMANCE DMC_FREQ_LEVEL_HIGH
SYS_STATUS_DUALVIEW DMC_FREQ_LEVEL_HIGH
>;
auto-min-freq = <324000>;
auto-freq-en = <1>;
#cooling-cells = <2>;
status = "disabled";
};
dmc_fsp: dmc-fsp {
compatible = "rockchip,rk3568-dmc-fsp";
debug_print_level = <0>;
ddr3_params = <&ddr3_params>;
ddr4_params = <&ddr4_params>;
lpddr3_params = <&lpddr3_params>;
lpddr4_params = <&lpddr4_params>;
lpddr4x_params = <&lpddr4x_params>;
status = "okay";
};
dmc_opp_table: dmc-opp-table {
compatible = "operating-points-v2";
mbist-vmin = <825000 900000 950000>;
nvmem-cells = <&log_leakage>, <&core_pvtm>, <&mbist_vmin>;
nvmem-cell-names = "leakage", "pvtm", "mbist-vmin";
rockchip,temp-hysteresis = <5000>;
rockchip,low-temp = <0>;
rockchip,low-temp-adjust-volt = <
/* MHz MHz uV */
0 1560 75000
>;
rockchip,leakage-voltage-sel = <
1 80 0
81 254 1
>;
rockchip,pvtm-voltage-sel = <
0 84000 0
84001 100000 1
>;
rockchip,pvtm-ch = <0 5>;
opp-1560000000 {
opp-hz = /bits/ 64 <1560000000>;
opp-microvolt = <900000>;
opp-microvolt-L0 = <900000>;
opp-microvolt-L1 = <850000>;
};
};
dmcdbg: dmcdbg {
compatible = "rockchip,rk3568-dmcdbg";
status = "disabled";
};
pcie2x1: pcie@fe260000 {
compatible = "rockchip,rk3568-pcie", "snps,dw-pcie";
#address-cells = <3>;
#size-cells = <2>;
bus-range = <0x0 0xf>;
clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>,
<&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>,
<&cru CLK_PCIE20_AUX_NDFT>;
clock-names = "aclk_mst", "aclk_slv",
"aclk_dbi", "pclk", "aux";
device_type = "pci";
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "sys", "pmc", "msg", "legacy", "err";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie2x1_intc 0>,
<0 0 0 2 &pcie2x1_intc 1>,
<0 0 0 3 &pcie2x1_intc 2>,
<0 0 0 4 &pcie2x1_intc 3>;
linux,pci-domain = <0>;
num-ib-windows = <6>;
num-viewport = <8>;
num-ob-windows = <2>;
max-link-speed = <2>;
msi-map = <0x0 &its 0x0 0x1000>;
num-lanes = <1>;
phys = <&combphy2_psq PHY_TYPE_PCIE>;
phy-names = "pcie-phy";
power-domains = <&power RK3568_PD_PIPE>;
ranges = <0x00000800 0x0 0xf4000000 0x0 0xf4000000 0x0 0x100000
0x81000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x100000
0x82000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x1e00000
0xc3000000 0x3 0x00000000 0x3 0x00000000 0x0 0x40000000>;
reg = <0x3 0xc0000000 0x0 0x400000>,
<0x0 0xfe260000 0x0 0x10000>;
reg-names = "pcie-dbi", "pcie-apb";
resets = <&cru SRST_PCIE20_POWERUP>;
reset-names = "pipe";
status = "disabled";
pcie2x1_intc: legacy-interrupt-controller {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>;
};
};
pcie3x1: pcie@fe270000 {
compatible = "rockchip,rk3568-pcie", "snps,dw-pcie";
#address-cells = <3>;
#size-cells = <2>;
bus-range = <0x10 0x1f>;
clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>,
<&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>,
<&cru CLK_PCIE30X1_AUX_NDFT>;
clock-names = "aclk_mst", "aclk_slv",
"aclk_dbi", "pclk", "aux";
device_type = "pci";
interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "sys", "pmc", "msg", "legacy", "err";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie3x1_intc 0>,
<0 0 0 2 &pcie3x1_intc 1>,
<0 0 0 3 &pcie3x1_intc 2>,
<0 0 0 4 &pcie3x1_intc 3>;
linux,pci-domain = <1>;
num-ib-windows = <6>;
num-ob-windows = <2>;
num-viewport = <8>;
max-link-speed = <3>;
msi-map = <0x1000 &its 0x1000 0x1000>;
num-lanes = <1>;
phys = <&pcie30phy>;
phy-names = "pcie-phy";
power-domains = <&power RK3568_PD_PIPE>;
ranges = <0x00000800 0x0 0xf2000000 0x0 0xf2000000 0x0 0x100000
0x81000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x100000
0x82000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x1e00000
0xc3000000 0x3 0x40000000 0x3 0x40000000 0x0 0x40000000>;
reg = <0x3 0xc0400000 0x0 0x400000>,
<0x0 0xfe270000 0x0 0x10000>;
reg-names = "pcie-dbi", "pcie-apb";
resets = <&cru SRST_PCIE30X1_POWERUP>;
reset-names = "pipe";
/* rockchip,bifurcation; lane1 when using 1+1 */
status = "disabled";
pcie3x1_intc: legacy-interrupt-controller {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;
};
};
pcie3x2: pcie@fe280000 {
compatible = "rockchip,rk3568-pcie", "snps,dw-pcie";
#address-cells = <3>;
#size-cells = <2>;
bus-range = <0x20 0x2f>;
clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>,
<&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>,
<&cru CLK_PCIE30X2_AUX_NDFT>;
clock-names = "aclk_mst", "aclk_slv",
"aclk_dbi", "pclk", "aux";
device_type = "pci";
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "sys", "pmc", "msg", "legacy", "err";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie3x2_intc 0>,
<0 0 0 2 &pcie3x2_intc 1>,
<0 0 0 3 &pcie3x2_intc 2>,
<0 0 0 4 &pcie3x2_intc 3>;
linux,pci-domain = <2>;
num-ib-windows = <6>;
num-viewport = <8>;
num-ob-windows = <2>;
max-link-speed = <3>;
msi-map = <0x2000 &its 0x2000 0x1000>;
num-lanes = <2>;
phys = <&pcie30phy>;
phy-names = "pcie-phy";
power-domains = <&power RK3568_PD_PIPE>;
ranges = <0x00000800 0x0 0xf0000000 0x0 0xf0000000 0x0 0x100000
0x81000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x100000
0x82000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x1e00000
0xc3000000 0x3 0x80000000 0x3 0x80000000 0x0 0x40000000>;
reg = <0x3 0xc0800000 0x0 0x400000>,
<0x0 0xfe280000 0x0 0x10000>;
reg-names = "pcie-dbi", "pcie-apb";
resets = <&cru SRST_PCIE30X2_POWERUP>;
reset-names = "pipe";
/* rockchip,bifurcation; lane0 when using 1+1 */
status = "disabled";
pcie3x2_intc: legacy-interrupt-controller {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 162 IRQ_TYPE_EDGE_RISING>;
};
};
gmac0: ethernet@fe2a0000 {
compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";
reg = <0x0 0xfe2a0000 0x0 0x10000>;
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq", "eth_wake_irq";
rockchip,grf = <&grf>;
clocks = <&cru SCLK_GMAC0>, <&cru SCLK_GMAC0_RX_TX>,
<&cru SCLK_GMAC0_RX_TX>, <&cru CLK_MAC0_REFOUT>,
<&cru ACLK_GMAC0>, <&cru PCLK_GMAC0>,
<&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>,
<&cru PCLK_XPCS>;
clock-names = "stmmaceth", "mac_clk_rx",
"mac_clk_tx", "clk_mac_refout",
"aclk_mac", "pclk_mac",
"clk_mac_speed", "ptp_ref",
"pclk_xpcs";
resets = <&cru SRST_A_GMAC0>;
reset-names = "stmmaceth";
snps,mixed-burst;
snps,tso;
snps,axi-config = <&gmac0_stmmac_axi_setup>;
snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
status = "disabled";
mdio0: mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <0x1>;
#size-cells = <0x0>;
};
gmac0_stmmac_axi_setup: stmmac-axi-config {
snps,wr_osr_lmt = <4>;
snps,rd_osr_lmt = <8>;
snps,blen = <0 0 0 0 16 8 4>;
};
gmac0_mtl_rx_setup: rx-queues-config {
snps,rx-queues-to-use = <1>;
queue0 {};
};
gmac0_mtl_tx_setup: tx-queues-config {
snps,tx-queues-to-use = <1>;
queue0 {};
};
};
sdmmc0: dwmmc@fe2b0000 {
compatible = "rockchip,rk3568-dw-mshc",
"rockchip,rk3288-dw-mshc";
reg = <0x0 0xfe2b0000 0x0 0x4000>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
max-frequency = <150000000>;
clocks = <&cru HCLK_SDMMC0>, <&cru CLK_SDMMC0>,
<&cru SCLK_SDMMC0_DRV>, <&cru SCLK_SDMMC0_SAMPLE>;
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
resets = <&cru SRST_SDMMC0>;
reset-names = "reset";
status = "disabled";
};
sdmmc1: dwmmc@fe2c0000 {
compatible = "rockchip,rk3568-dw-mshc",
"rockchip,rk3288-dw-mshc";
reg = <0x0 0xfe2c0000 0x0 0x4000>;
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
max-frequency = <150000000>;
clocks = <&cru HCLK_SDMMC1>, <&cru CLK_SDMMC1>,
<&cru SCLK_SDMMC1_DRV>, <&cru SCLK_SDMMC1_SAMPLE>;
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
resets = <&cru SRST_SDMMC1>;
reset-names = "reset";
status = "disabled";
};
sfc: sfc@fe300000 {
compatible = "rockchip,sfc";
reg = <0x0 0xfe300000 0x0 0x4000>;
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
clock-names = "clk_sfc", "hclk_sfc";
assigned-clocks = <&cru SCLK_SFC>;
assigned-clock-rates = <100000000>;
status = "disabled";
};
sdhci: sdhci@fe310000 {
compatible = "rockchip,dwcmshc-sdhci", "snps,dwcmshc-sdhci";
reg = <0x0 0xfe310000 0x0 0x10000>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>,
<&cru CCLK_EMMC>;
assigned-clock-rates = <200000000>, <24000000>, <200000000>;
clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>,
<&cru ACLK_EMMC>, <&cru BCLK_EMMC>,
<&cru TCLK_EMMC>;
clock-names = "core", "bus", "axi", "block", "timer";
status = "disabled";
};
nandc0: nandc@fe330000 {
compatible = "rockchip,rk-nandc-v9";
reg = <0x0 0xfe330000 0x0 0x4000>;
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
nandc_id = <0>;
clocks = <&cru NCLK_NANDC>, <&cru HCLK_NANDC>;
clock-names = "clk_nandc", "hclk_nandc";
status = "disabled";
};
crypto: crypto@fe380000 {
compatible = "rockchip,rk3568-crypto";
reg = <0x0 0xfe380000 0x0 0x4000>;
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_CRYPTO_NS>, <&cru HCLK_CRYPTO_NS>,
<&cru CLK_CRYPTO_NS_CORE>, <&cru CLK_CRYPTO_NS_PKA>;
clock-names = "aclk", "hclk", "sclk", "apb_pclk";
assigned-clocks = <&cru CLK_CRYPTO_NS_CORE>;
assigned-clock-rates = <200000000>;
resets = <&cru SRST_CRYPTO_NS_CORE>;
reset-names = "crypto-rst";
status = "disabled";
};
rng: rng@fe388000 {
compatible = "rockchip,cryptov2-rng";
reg = <0x0 0xfe388000 0x0 0x2000>;
clocks = <&cru CLK_TRNG_NS>, <&cru HCLK_TRNG_NS>;
clock-names = "clk_trng", "hclk_trng";
resets = <&cru SRST_TRNG_NS>;
reset-names = "reset";
status = "disabled";
};
otp: otp@fe38c000 {
compatible = "rockchip,rk3568-otp";
reg = <0x0 0xfe38c000 0x0 0x4000>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&cru CLK_OTPC_NS_USR>, <&cru CLK_OTPC_NS_SBPI>,
<&cru PCLK_OTPC_NS>, <&cru PCLK_OTPPHY>;
clock-names = "usr", "sbpi", "apb", "phy";
resets = <&cru SRST_OTPPHY>;
reset-names = "otp_phy";
/* Data cells */
cpu_code: cpu-code@2 {
reg = <0x02 0x2>;
};
otp_cpu_version: cpu-version@8 {
reg = <0x08 0x1>;
bits = <3 3>;
};
mbist_vmin: mbist-vmin@9 {
reg = <0x09 0x1>;
bits = <0 4>;
};
otp_id: id@a {
reg = <0x0a 0x10>;
};
cpu_leakage: cpu-leakage@1a {
reg = <0x1a 0x1>;
};
log_leakage: log-leakage@1b {
reg = <0x1b 0x1>;
};
npu_leakage: npu-leakage@1c {
reg = <0x1c 0x1>;
};
gpu_leakage: gpu-leakage@1d {
reg = <0x1d 0x1>;
};
core_pvtm:core-pvtm@2a {
reg = <0x2a 0x2>;
};
};
i2s0_8ch: i2s@fe400000 {
compatible = "rockchip,rk3568-i2s-tdm";
reg = <0x0 0xfe400000 0x0 0x1000>;
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>;
clock-names = "mclk_tx", "mclk_rx", "hclk";
dmas = <&dmac1 0>;
dma-names = "tx";
resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>;
reset-names = "tx-m", "rx-m";
rockchip,cru = <&cru>;
rockchip,grf = <&grf>;
rockchip,playback-only;
#sound-dai-cells = <0>;
status = "disabled";
};
i2s1_8ch: i2s@fe410000 {
compatible = "rockchip,rk3568-i2s-tdm";
reg = <0x0 0xfe410000 0x0 0x1000>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, <&cru HCLK_I2S1_8CH>;
clock-names = "mclk_tx", "mclk_rx", "hclk";
dmas = <&dmac1 2>, <&dmac1 3>;
dma-names = "tx", "rx";
resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>;
reset-names = "tx-m", "rx-m";
rockchip,cru = <&cru>;
rockchip,grf = <&grf>;
#sound-dai-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&i2s1m0_sclktx
&i2s1m0_sclkrx
&i2s1m0_lrcktx
&i2s1m0_lrckrx
&i2s1m0_sdi0
&i2s1m0_sdi1
&i2s1m0_sdi2
&i2s1m0_sdi3
&i2s1m0_sdo0
&i2s1m0_sdo1
&i2s1m0_sdo2
&i2s1m0_sdo3>;
status = "disabled";
};
i2s2_2ch: i2s@fe420000 {
compatible = "rockchip,rk3568-i2s-tdm";
reg = <0x0 0xfe420000 0x0 0x1000>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru MCLK_I2S2_2CH>, <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>;
clock-names = "mclk_tx", "mclk_rx", "hclk";
dmas = <&dmac1 4>, <&dmac1 5>;
dma-names = "tx", "rx";
rockchip,cru = <&cru>;
rockchip,grf = <&grf>;
rockchip,clk-trcm = <1>;
#sound-dai-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&i2s2m0_sclktx
&i2s2m0_lrcktx
&i2s2m0_sdi
&i2s2m0_sdo>;
status = "disabled";
};
i2s3_2ch: i2s@fe430000 {
compatible = "rockchip,rk3568-i2s-tdm";
reg = <0x0 0xfe430000 0x0 0x1000>;
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru MCLK_I2S3_2CH_TX>, <&cru MCLK_I2S3_2CH_RX>, <&cru HCLK_I2S3_2CH>;
clock-names = "mclk_tx", "mclk_rx", "hclk";
dmas = <&dmac1 6>, <&dmac1 7>;
dma-names = "tx", "rx";
resets = <&cru SRST_M_I2S3_2CH_TX>, <&cru SRST_M_I2S3_2CH_RX>;
reset-names = "tx-m", "rx-m";
rockchip,cru = <&cru>;
rockchip,grf = <&grf>;
rockchip,clk-trcm = <1>;
#sound-dai-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&i2s3m0_sclk
&i2s3m0_lrck
&i2s3m0_sdi
&i2s3m0_sdo>;
status = "disabled";
};
pdm: pdm@fe440000 {
compatible = "rockchip,rk3568-pdm";
reg = <0x0 0xfe440000 0x0 0x1000>;
clocks = <&cru MCLK_PDM>, <&cru HCLK_PDM>;
clock-names = "pdm_clk", "pdm_hclk";
dmas = <&dmac1 9>;
dma-names = "rx";
pinctrl-names = "default";
pinctrl-0 = <&pdmm0_clk
&pdmm0_clk1
&pdmm0_sdi0
&pdmm0_sdi1
&pdmm0_sdi2
&pdmm0_sdi3>;
#sound-dai-cells = <0>;
status = "disabled";
};
vad: vad@fe450000 {
compatible = "rockchip,rk3568-vad";
reg = <0x0 0xfe450000 0x0 0x10000>;
reg-names = "vad";
clocks = <&cru HCLK_VAD>;
clock-names = "hclk";
interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
rockchip,audio-src = <0>;
rockchip,det-channel = <0>;
rockchip,mode = <0>;
#sound-dai-cells = <0>;
status = "disabled";
};
spdif_8ch: spdif@fe460000 {
compatible = "rockchip,rk3568-spdif";
reg = <0x0 0xfe460000 0x0 0x1000>;
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&dmac1 1>;
dma-names = "tx";
clock-names = "mclk", "hclk";
clocks = <&cru MCLK_SPDIF_8CH>, <&cru HCLK_SPDIF_8CH>;
#sound-dai-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&spdifm0_tx>;
status = "disabled";
};
audpwm: audpwm@fe470000 {
compatible = "rockchip,rk3568-audio-pwm", "rockchip,audio-pwm-v1";
reg = <0x0 0xfe470000 0x0 0x1000>;
clocks = <&cru SCLK_AUDPWM>, <&cru HCLK_AUDPWM>;
clock-names = "clk", "hclk";
dmas = <&dmac1 8>;
dma-names = "tx";
#sound-dai-cells = <0>;
rockchip,sample-width-bits = <11>;
rockchip,interpolat-points = <1>;
status = "disabled";
};
dig_acodec: codec-digital@fe478000 {
compatible = "rockchip,rk3568-codec-digital", "rockchip,codec-digital-v1";
reg = <0x0 0xfe478000 0x0 0x1000>;
clocks = <&cru CLK_ACDCDIG_ADC>, <&cru CLK_ACDCDIG_DAC>,
<&cru CLK_ACDCDIG_I2C>, <&cru HCLK_ACDCDIG>;
clock-names = "adc", "dac", "i2c", "pclk";
pinctrl-names = "default";
pinctrl-0 = <&acodec_pins>;
resets = <&cru SRST_ACDCDIG>;
reset-names = "reset" ;
rockchip,grf = <&grf>;
#sound-dai-cells = <0>;
status = "disabled";
};
dmac0: dmac@fe530000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x0 0xfe530000 0x0 0x4000>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_BUS>;
clock-names = "apb_pclk";
#dma-cells = <1>;
arm,pl330-periph-burst;
};
dmac1: dmac@fe550000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x0 0xfe550000 0x0 0x4000>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_BUS>;
clock-names = "apb_pclk";
#dma-cells = <1>;
arm,pl330-periph-burst;
};
scr: rkscr@fe560000 {
compatible = "rockchip-scr";
reg = <0x0 0xfe560000 0x0 0x10000>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&scr_pins>;
clocks = <&cru PCLK_SCR>;
clock-names = "g_pclk_sim_card";
status = "disabled";
};
can0: can@fe570000 {
compatible = "rockchip,rk3568-can-2.0";
reg = <0x0 0xfe570000 0x0 0x1000>;
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru CLK_CAN0>, <&cru PCLK_CAN0>;
clock-names = "baudclk", "apb_pclk";
resets = <&cru SRST_CAN0>, <&cru SRST_P_CAN0>;
reset-names = "can", "can-apb";
tx-fifo-depth = <1>;
rx-fifo-depth = <6>;
status = "disabled";
};
can1: can@fe580000 {
compatible = "rockchip,rk3568-can-2.0";
reg = <0x0 0xfe580000 0x0 0x1000>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru CLK_CAN1>, <&cru PCLK_CAN1>;
clock-names = "baudclk", "apb_pclk";
resets = <&cru SRST_CAN1>, <&cru SRST_P_CAN1>;
reset-names = "can", "can-apb";
tx-fifo-depth = <1>;
rx-fifo-depth = <6>;
status = "disabled";
};
can2: can@fe590000 {
compatible = "rockchip,rk3568-can-2.0";
reg = <0x0 0xfe590000 0x0 0x1000>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru CLK_CAN2>, <&cru PCLK_CAN2>;
clock-names = "baudclk", "apb_pclk";
resets = <&cru SRST_CAN2>, <&cru SRST_P_CAN2>;
reset-names = "can", "can-apb";
tx-fifo-depth = <1>;
rx-fifo-depth = <6>;
status = "disabled";
};
i2c1: i2c@fe5a0000 {
compatible = "rockchip,rk3399-i2c";
reg = <0x0 0xfe5a0000 0x0 0x1000>;
clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
clock-names = "i2c", "pclk";
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&i2c1_xfer>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c2: i2c@fe5b0000 {
compatible = "rockchip,rk3399-i2c";
reg = <0x0 0xfe5b0000 0x0 0x1000>;
clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>;
clock-names = "i2c", "pclk";
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&i2c2m0_xfer>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c3: i2c@fe5c0000 {
compatible = "rockchip,rk3399-i2c";
reg = <0x0 0xfe5c0000 0x0 0x1000>;
clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
clock-names = "i2c", "pclk";
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&i2c3m0_xfer>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c4: i2c@fe5d0000 {
compatible = "rockchip,rk3399-i2c";
reg = <0x0 0xfe5d0000 0x0 0x1000>;
clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
clock-names = "i2c", "pclk";
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&i2c4m0_xfer>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c5: i2c@fe5e0000 {
compatible = "rockchip,rk3399-i2c";
reg = <0x0 0xfe5e0000 0x0 0x1000>;
clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>;
clock-names = "i2c", "pclk";
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&i2c5m0_xfer>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
rktimer: timer@fe5f0000 {
compatible = "rockchip,rk3568-timer", "rockchip,rk3288-timer";
reg = <0x0 0xfe5f0000 0x0 0x1000>;
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_TIMER>, <&cru CLK_TIMER0>;
clock-names = "pclk", "timer";
};
wdt: watchdog@fe600000 {
compatible = "snps,dw-wdt";
reg = <0x0 0xfe600000 0x0 0x100>;
clocks = <&cru TCLK_WDT_NS>, <&cru PCLK_WDT_NS>;
clock-names = "tclk", "pclk";
interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
status = "okay";
};
spi0: spi@fe610000 {
compatible = "rockchip,rk3066-spi";
reg = <0x0 0xfe610000 0x0 0x1000>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>;
clock-names = "spiclk", "apb_pclk";
dmas = <&dmac0 20>, <&dmac0 21>;
dma-names = "tx", "rx";
pinctrl-names = "default", "high_speed";
pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>;
pinctrl-1 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins_hs>;
status = "disabled";
};
spi1: spi@fe620000 {
compatible = "rockchip,rk3066-spi";
reg = <0x0 0xfe620000 0x0 0x1000>;
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>;
clock-names = "spiclk", "apb_pclk";
dmas = <&dmac0 22>, <&dmac0 23>;
dma-names = "tx", "rx";
pinctrl-names = "default", "high_speed";
pinctrl-0 = <&spi1m0_cs0 &spi1m0_cs1 &spi1m0_pins>;
pinctrl-1 = <&spi1m0_cs0 &spi1m0_cs1 &spi1m0_pins_hs>;
status = "disabled";
};
spi2: spi@fe630000 {
compatible = "rockchip,rk3066-spi";
reg = <0x0 0xfe630000 0x0 0x1000>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>;
clock-names = "spiclk", "apb_pclk";
dmas = <&dmac0 24>, <&dmac0 25>;
dma-names = "tx", "rx";
pinctrl-names = "default", "high_speed";
pinctrl-0 = <&spi2m0_cs0 &spi2m0_cs1 &spi2m0_pins>;
pinctrl-1 = <&spi2m0_cs0 &spi2m0_cs1 &spi2m0_pins_hs>;
status = "disabled";
};
spi3: spi@fe640000 {
compatible = "rockchip,rk3066-spi";
reg = <0x0 0xfe640000 0x0 0x1000>;
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>;
clock-names = "spiclk", "apb_pclk";
dmas = <&dmac0 26>, <&dmac0 27>;
dma-names = "tx", "rx";
pinctrl-names = "default", "high_speed";
pinctrl-0 = <&spi3m0_cs0 &spi3m0_cs1 &spi3m0_pins>;
pinctrl-1 = <&spi3m0_cs0 &spi3m0_cs1 &spi3m0_pins_hs>;
status = "disabled";
};
uart1: serial@fe650000 {
compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
reg = <0x0 0xfe650000 0x0 0x100>;
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
dmas = <&dmac0 2>, <&dmac0 3>;
pinctrl-names = "default";
pinctrl-0 = <&uart1m0_xfer>;
status = "disabled";
};
uart2: serial@fe660000 {
compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
reg = <0x0 0xfe660000 0x0 0x100>;
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
dmas = <&dmac0 4>, <&dmac0 5>;
pinctrl-names = "default";
pinctrl-0 = <&uart2m0_xfer>;
status = "disabled";
};
uart3: serial@fe670000 {
compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
reg = <0x0 0xfe670000 0x0 0x100>;
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
dmas = <&dmac0 6>, <&dmac0 7>;
pinctrl-names = "default";
pinctrl-0 = <&uart3m0_xfer>;
status = "disabled";
};
uart4: serial@fe680000 {
compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
reg = <0x0 0xfe680000 0x0 0x100>;
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
dmas = <&dmac0 8>, <&dmac0 9>;
pinctrl-names = "default";
pinctrl-0 = <&uart4m0_xfer>;
status = "disabled";
};
uart5: serial@fe690000 {
compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
reg = <0x0 0xfe690000 0x0 0x100>;
interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
dmas = <&dmac0 10>, <&dmac0 11>;
pinctrl-names = "default";
pinctrl-0 = <&uart5m0_xfer>;
status = "disabled";
};
uart6: serial@fe6a0000 {
compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
reg = <0x0 0xfe6a0000 0x0 0x100>;
interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>;
clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
dmas = <&dmac0 12>, <&dmac0 13>;
pinctrl-names = "default";
pinctrl-0 = <&uart6m0_xfer>;
status = "disabled";
};
uart7: serial@fe6b0000 {
compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
reg = <0x0 0xfe6b0000 0x0 0x100>;
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>;
clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
dmas = <&dmac0 14>, <&dmac0 15>;
pinctrl-names = "default";
pinctrl-0 = <&uart7m0_xfer>;
status = "disabled";
};
uart8: serial@fe6c0000 {
compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
reg = <0x0 0xfe6c0000 0x0 0x100>;
interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>;
clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
dmas = <&dmac0 16>, <&dmac0 17>;
pinctrl-names = "default";
pinctrl-0 = <&uart8m0_xfer>;
status = "disabled";
};
uart9: serial@fe6d0000 {
compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
reg = <0x0 0xfe6d0000 0x0 0x100>;
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>;
clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
dmas = <&dmac0 18>, <&dmac0 19>;
pinctrl-names = "default";
pinctrl-0 = <&uart9m0_xfer>;
status = "disabled";
};
pwm4: pwm@fe6e0000 {
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
reg = <0x0 0xfe6e0000 0x0 0x10>;
#pwm-cells = <3>;
pinctrl-names = "active";
pinctrl-0 = <&pwm4_pins>;
clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
clock-names = "pwm", "pclk";
status = "disabled";
};
pwm5: pwm@fe6e0010 {
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
reg = <0x0 0xfe6e0010 0x0 0x10>;
#pwm-cells = <3>;
pinctrl-names = "active";
pinctrl-0 = <&pwm5_pins>;
clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
clock-names = "pwm", "pclk";
status = "disabled";
};
pwm6: pwm@fe6e0020 {
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
reg = <0x0 0xfe6e0020 0x0 0x10>;
#pwm-cells = <3>;
pinctrl-names = "active";
pinctrl-0 = <&pwm6_pins>;
clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
clock-names = "pwm", "pclk";
status = "disabled";
};
pwm7: pwm@fe6e0030 {
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
reg = <0x0 0xfe6e0030 0x0 0x10>;
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
#pwm-cells = <3>;
pinctrl-names = "active";
pinctrl-0 = <&pwm7_pins>;
clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
clock-names = "pwm", "pclk";
status = "disabled";
};
pwm8: pwm@fe6f0000 {
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
reg = <0x0 0xfe6f0000 0x0 0x10>;
#pwm-cells = <3>;
pinctrl-names = "active";
pinctrl-0 = <&pwm8m0_pins>;
clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
clock-names = "pwm", "pclk";
status = "disabled";
};
pwm9: pwm@fe6f0010 {
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
reg = <0x0 0xfe6f0010 0x0 0x10>;
#pwm-cells = <3>;
pinctrl-names = "active";
pinctrl-0 = <&pwm9m0_pins>;
clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
clock-names = "pwm", "pclk";
status = "disabled";
};
pwm10: pwm@fe6f0020 {
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
reg = <0x0 0xfe6f0020 0x0 0x10>;
#pwm-cells = <3>;
pinctrl-names = "active";
pinctrl-0 = <&pwm10m0_pins>;
clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
clock-names = "pwm", "pclk";
status = "disabled";
};
pwm11: pwm@fe6f0030 {
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
reg = <0x0 0xfe6f0030 0x0 0x10>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
#pwm-cells = <3>;
pinctrl-names = "active";
pinctrl-0 = <&pwm11m0_pins>;
clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
clock-names = "pwm", "pclk";
status = "disabled";
};
pwm12: pwm@fe700000 {
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
reg = <0x0 0xfe700000 0x0 0x10>;
#pwm-cells = <3>;
pinctrl-names = "active";
pinctrl-0 = <&pwm12m0_pins>;
clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
clock-names = "pwm", "pclk";
status = "disabled";
};
pwm13: pwm@fe700010 {
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
reg = <0x0 0xfe700010 0x0 0x10>;
#pwm-cells = <3>;
pinctrl-names = "active";
pinctrl-0 = <&pwm13m0_pins>;
clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
clock-names = "pwm", "pclk";
status = "disabled";
};
pwm14: pwm@fe700020 {
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
reg = <0x0 0xfe700020 0x0 0x10>;
#pwm-cells = <3>;
pinctrl-names = "active";
pinctrl-0 = <&pwm14m0_pins>;
clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
clock-names = "pwm", "pclk";
status = "disabled";
};
pwm15: pwm@fe700030 {
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
reg = <0x0 0xfe700030 0x0 0x10>;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
#pwm-cells = <3>;
pinctrl-names = "active";
pinctrl-0 = <&pwm15m0_pins>;
clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
clock-names = "pwm", "pclk";
status = "disabled";
};
tsadc: tsadc@fe710000 {
compatible = "rockchip,rk3568-tsadc";
reg = <0x0 0xfe710000 0x0 0x100>;
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
rockchip,grf = <&grf>;
clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>;
clock-names = "tsadc", "apb_pclk";
assigned-clocks = <&cru CLK_TSADC_TSEN>, <&cru CLK_TSADC>;
assigned-clock-rates = <17000000>, <700000>;
resets = <&cru SRST_TSADC>, <&cru SRST_P_TSADC>,
<&cru SRST_TSADCPHY>;
reset-names = "tsadc", "tsadc-apb", "tsadc-phy";
#thermal-sensor-cells = <1>;
rockchip,hw-tshut-temp = <120000>;
rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
pinctrl-names = "gpio", "otpout";
pinctrl-0 = <&tsadc_gpio_func>;
pinctrl-1 = <&tsadc_shutorg>;
status = "disabled";
};
saradc: saradc@fe720000 {
compatible = "rockchip,rk3568-saradc", "rockchip,rk3399-saradc";
reg = <0x0 0xfe720000 0x0 0x100>;
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
#io-channel-cells = <1>;
clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
clock-names = "saradc", "apb_pclk";
resets = <&cru SRST_P_SARADC>;
reset-names = "saradc-apb";
status = "disabled";
};
mailbox: mailbox@fe780000 {
compatible = "rockchip,rk3568-mailbox",
"rockchip,rk3368-mailbox";
reg = <0x0 0xfe780000 0x0 0x1000>;
interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_MAILBOX>;
clock-names = "pclk_mailbox";
#mbox-cells = <1>;
status = "disabled";
};
combphy0_us: phy@fe820000 {
compatible = "rockchip,rk3568-naneng-combphy";
reg = <0x0 0xfe820000 0x0 0x100>;
#phy-cells = <1>;
clocks = <&pmucru CLK_PCIEPHY0_REF>, <&cru PCLK_PIPEPHY0>,
<&cru PCLK_PIPE>;
clock-names = "refclk", "apbclk", "pipe_clk";
assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>;
assigned-clock-rates = <100000000>;
resets = <&cru SRST_P_PIPEPHY0>, <&cru SRST_PIPEPHY0>;
reset-names = "combphy-apb", "combphy";
rockchip,pipe-grf = <&pipegrf>;
rockchip,pipe-phy-grf = <&pipe_phy_grf0>;
status = "disabled";
};
combphy1_usq: phy@fe830000 {
compatible = "rockchip,rk3568-naneng-combphy";
reg = <0x0 0xfe830000 0x0 0x100>;
#phy-cells = <1>;
clocks = <&pmucru CLK_PCIEPHY1_REF>, <&cru PCLK_PIPEPHY1>,
<&cru PCLK_PIPE>;
clock-names = "refclk", "apbclk", "pipe_clk";
assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>;
assigned-clock-rates = <100000000>;
resets = <&cru SRST_P_PIPEPHY1>, <&cru SRST_PIPEPHY1>;
reset-names = "combphy-apb", "combphy";
rockchip,pipe-grf = <&pipegrf>;
rockchip,pipe-phy-grf = <&pipe_phy_grf1>;
status = "disabled";
};
combphy2_psq: phy@fe840000 {
compatible = "rockchip,rk3568-naneng-combphy";
reg = <0x0 0xfe840000 0x0 0x100>;
#phy-cells = <1>;
clocks = <&pmucru CLK_PCIEPHY2_REF>, <&cru PCLK_PIPEPHY2>,
<&cru PCLK_PIPE>;
clock-names = "refclk", "apbclk", "pipe_clk";
assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>;
assigned-clock-rates = <100000000>;
resets = <&cru SRST_P_PIPEPHY2>, <&cru SRST_PIPEPHY2>;
reset-names = "combphy-apb", "combphy";
rockchip,pipe-grf = <&pipegrf>;
rockchip,pipe-phy-grf = <&pipe_phy_grf2>;
status = "disabled";
};
video_phy0: video-phy@fe850000 {
compatible = "rockchip,rk3568-video-phy";
reg = <0x0 0xfe850000 0x0 0x10000>,
<0x0 0xfe060000 0x0 0x10000>;
clocks = <&pmucru CLK_MIPIDSIPHY0_REF>,
<&cru PCLK_MIPIDSIPHY0>, <&cru PCLK_DSITX_0>;
clock-names = "ref", "pclk_phy", "pclk_host";
#clock-cells = <0>;
resets = <&cru SRST_P_MIPIDSIPHY0>;
reset-names = "rst";
power-domains = <&power RK3568_PD_VO>;
#phy-cells = <0>;
status = "disabled";
};
video_phy1: video-phy@fe860000 {
compatible = "rockchip,rk3568-video-phy";
reg = <0x0 0xfe860000 0x0 0x10000>,
<0x0 0xfe070000 0x0 0x10000>;
clocks = <&pmucru CLK_MIPIDSIPHY1_REF>,
<&cru PCLK_MIPIDSIPHY1>, <&cru PCLK_DSITX_1>;
clock-names = "ref", "pclk_phy", "pclk_host";
#clock-cells = <0>;
resets = <&cru SRST_P_MIPIDSIPHY1>;
reset-names = "rst";
power-domains = <&power RK3568_PD_VO>;
#phy-cells = <0>;
status = "disabled";
};
csi2_dphy_hw: csi2-dphy-hw@fe870000 {
compatible = "rockchip,rk3568-csi2-dphy-hw";
reg = <0x0 0xfe870000 0x0 0x1000>;
clocks = <&cru PCLK_MIPICSIPHY>;
clock-names = "pclk";
rockchip,grf = <&grf>;
status = "disabled";
};
/*
* csi2_dphy0: used for csi2 dphy full mode,
is mutually exclusive with
csi2_dphy1 and csi2_dphy2
* csi2_dphy1: used for csi2 dphy split mode,
physical lanes use lane0 and lane1,
can be used with csi2_dphy2 parallel
* csi2_dphy2: used for csi2 dphy split mode,
physical lanes use lane2 and lane3,
can be used with csi2_dphy1 parallel
*/
csi2_dphy0: csi2-dphy0 {
compatible = "rockchip,rk3568-csi2-dphy";
rockchip,hw = <&csi2_dphy_hw>;
status = "disabled";
};
csi2_dphy1: csi2-dphy1 {
compatible = "rockchip,rk3568-csi2-dphy";
rockchip,hw = <&csi2_dphy_hw>;
status = "disabled";
};
csi2_dphy2: csi2-dphy2 {
compatible = "rockchip,rk3568-csi2-dphy";
rockchip,hw = <&csi2_dphy_hw>;
status = "disabled";
};
usb2phy0: usb2-phy@fe8a0000 {
compatible = "rockchip,rk3568-usb2phy";
reg = <0x0 0xfe8a0000 0x0 0x10000>;
interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pmucru CLK_USBPHY0_REF>;
clock-names = "phyclk";
#clock-cells = <0>;
assigned-clocks = <&cru USB480M>;
assigned-clock-parents = <&usb2phy0>;
clock-output-names = "usb480m_phy";
rockchip,usbgrf = <&usb2phy0_grf>;
status = "disabled";
u2phy0_host: host-port {
#phy-cells = <0>;
status = "disabled";
};
u2phy0_otg: otg-port {
#phy-cells = <0>;
status = "disabled";
};
};
usb2phy1: usb2-phy@fe8b0000 {
compatible = "rockchip,rk3568-usb2phy";
reg = <0x0 0xfe8b0000 0x0 0x10000>;
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pmucru CLK_USBPHY1_REF>;
clock-names = "phyclk";
#clock-cells = <0>;
rockchip,usbgrf = <&usb2phy1_grf>;
status = "disabled";
u2phy1_host: host-port {
#phy-cells = <0>;
status = "disabled";
};
u2phy1_otg: otg-port {
#phy-cells = <0>;
status = "disabled";
};
};
pcie30phy: phy@fe8c0000 {
compatible = "rockchip,rk3568-pcie3-phy";
reg = <0x0 0xfe8c0000 0x0 0x20000>;
#phy-cells = <0>;
clocks = <&pmucru CLK_PCIE30PHY_REF_M>, <&pmucru CLK_PCIE30PHY_REF_N>,
<&cru PCLK_PCIE30PHY>;
clock-names = "refclk_m", "refclk_n", "pclk";
resets = <&cru SRST_PCIE30PHY>;
reset-names = "phy";
rockchip,phy-grf = <&pcie30_phy_grf>;
status = "disabled";
};
pinctrl: pinctrl {
compatible = "rockchip,rk3568-pinctrl";
rockchip,grf = <&grf>;
rockchip,pmu = <&pmugrf>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
gpio0: gpio@fdd60000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xfdd60000 0x0 0x100>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl 0 0 32>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio1: gpio@fe740000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xfe740000 0x0 0x100>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl 0 32 32>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio2: gpio@fe750000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xfe750000 0x0 0x100>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl 0 64 32>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio3: gpio@fe760000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xfe760000 0x0 0x100>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl 0 96 32>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio4: gpio@fe770000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xfe770000 0x0 0x100>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl 0 128 32>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
};
#include "rk3568-pinctrl.dtsi"
3.2 设备节点
设备树是采用树形结构来描述板子上的设备信息的文件，每个设备都是一个节点，叫做设备节点，每个节点都通过一些属性信息来描述节点信息，属性就是键值对。以下文件是结合RK官方的设备树缩减出来设备树文件内容：
/{
compatible = "rockchip,rk3568";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
aliases{
serial0=&uart0;
}
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x0>;
enable-method = "psci";
clocks = <&scmi_clk 0>;
operating-points-v2 = <&cpu0_opp_table>;
cpu-idle-states = <&CPU_SLEEP>;
#cooling-cells = <2>;
dynamic-power-coefficient = <187>;
};
cpu1: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x100>;
enable-method = "psci";
clocks = <&scmi_clk 0>;
operating-points-v2 = <&cpu0_opp_table>;
cpu-idle-states = <&CPU_SLEEP>;
};
cpu2: cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x200>;
enable-method = "psci";
clocks = <&scmi_clk 0>;
operating-points-v2 = <&cpu0_opp_table>;
cpu-idle-states = <&CPU_SLEEP>;
};
cpu3: cpu@300 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x300>;
enable-method = "psci";
clocks = <&scmi_clk 0>;
operating-points-v2 = <&cpu0_opp_table>;
cpu-idle-states = <&CPU_SLEEP>;
};
i2c0: i2c@fdd40000 {
compatible = "rockchip,rk3399-i2c";
reg = <0x0 0xfdd40000 0x0 0x1000>;
clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>;
clock-names = "i2c", "pclk";
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&i2c0_xfer>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
}
1. 节点命名格式
设备树中节点命名格式如下：
node-name@unit-address
node-name是节点名字，是ASCII字符串。
unit-address是设备的地址或寄存器首地址
另一种命名方式
label: node-name@unit-address
例如 cpu0:cpu@0，引入label是为了方便节点访问
2. 设备树常用的数据形式
字符串
compatible="rockchip,rk3568"
32位无符号数
reg=<0>
数组值
reg=<0,0x12345,100>
字符串列表
compatible = "rockchip,rk3568-evb ", "rockchip,rk3568";
3.3 标准属性
1. compatible
compatible属性也叫做“兼容性”属性，这是非常重要的一个属性！ compatible属性的值是一个字符串列表， compatible属性用于将设备和驱动绑定起来。字符串列表用于选择设备所要使用的驱动程序， compatible属性值的格式如下所示：
"manufacturer,model"
其中 manufacturer表示厂商， model一般是模块对应的驱动名字。比如 rk3568-atk-evb1-ddr4-v10.dtsi中有一个 MIPI摄像头 节点，这个节点的 摄像头 芯片采用的 SONY公司出品的 IMX415 compatible属性值如下：
compatible = "sony,imx415";
属性值为“ sony,imx415”，其中 sony’表示厂商是 sony，也就是索尼 imx415”表示驱动模块名字。
compatible也可以多个属性值。比如：
compatible = "ilitek,ili9881d", "simple-panel-dsi";
这样设备就有两个属性值，这个设备首先使用第一个兼容值在 Linux内核里面查找，看看能不能找到与之匹配的驱动文件，如果没有找到的话就使用第二个兼容值查，以此类推，直到查找完 compatible属性中的所有值。
一般驱动程序文件都会有一个 OF匹配表，此 OF匹配表保存着一些 compatible值，如果设备节点的 compatible属性值和 OF匹配表中的任何一个值相等，那么就表示设备可以使用这个驱动。比如在文件 imx415.c中有如下内容：
static const struct of_device_id imx415_of_match[] = {
{.compatible="sony.imx415"},
{},
}
2. model属性
model属性值也是一个字符串，一般 model属性描述开发板的名字或者设备模块信息
model = "Rockchip rk3568 EVB DDR4 V10 Board";
3. status属性
status属性看名字就知道是和设备状态有关的， status属性值也是字符串，字符串是设备的状态信息，可选的状态如表
| 值 | 描述 |
|---|---|
| "okey" | 表明设备是可操作的。 |
| "disabled" | 表明设备当前是不可操作的，但是在未来可以变为可操作的，比如热插拔设备插入以后。至于 disabled的具体含义还要看设备的绑定文档。 |
| "fail" | 表明设备不可操作，设备检测到了一系列的错误，而且设备也不大可能变得可操作 |
| "fail-sss" | 含义和“fail”相同，后面的 sss部分是检测到的错误内容。 |
4. #address-cells和#size-cells属性
这两个属性的值都是无符号 32位整形， #address-cells和 #size-cells这两个属性可以用在任何拥有子节点的设备中，用于描述子节点的地址信息。
#address-cells属性值决定了子节点 reg属性中地址信息所占用的字长 (32位 )，，#size-cells属性值决定了子节点 reg属性中长度信息所占的字长 (32位 )。
#address-cells和 #size-cells表明了子节点应该如何编写 reg属性值，一般 reg属性
都是和地址有关的内容，和地址相关的信息有两种：起始地址和地址长度。
reg属性的格式为：
reg = <address1 length1 address2 length2 address3 length3…………>
5. reg属性
属性前面已经提到过了， reg属性的值一般是 (address length)对。 reg属性一般用于描述设备地址空间资源信息或者设备地址信息，比如某个外设的寄存器地址范围信息，或者 IIC器件的设备地址等，比如在 rk3568.dtsi中有如下内容：
uart5: serial@fe690000 {
compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
reg = <0x0 0xfe690000 0x0 0x100>;
interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
dmas = <&dmac0 10>, <&dmac0 11>;
pinctrl-names = "default";
pinctrl-0 = <&uart5m0_xfer>;
status = "disabled";
};
uart5节点描述了 rk3568系列芯片的 UART5相关信息，重点是第 3104行的 reg属性。由于 uart5的父节点“ “/”设置了 #address-cells = <1>、 #size-cells = <1>，因此 reg属性中address=0xff5a0000 length=0x100。查阅《 Rockchip RK3568 TRM Part1》可知， RK3568芯片的UART5寄存器首地址为 0xfe690000 长度为 64KB 但是 UART5的 寄存器远远用不了 64KB，0X100完全够了， 这里我们重点是获取 UART5寄存器首地址 。
6. ranges 属性
ranges属性值可以为空或者按照 (child-bus-address,parent-bus-address,length)格式编写的数字矩阵， ranges是一个地址映射 /转换表， ranges属性每个项目由子地址、父地址和地址空间长度这三部分组成：
| item | 描述 |
|---|---|
| child-bus-address | 子总线地址空间的物理地址，由父节点的 #address-cells确定此物理地址所占用的字长。 |
| parent-bus-address | 父总线地址空间的物理地址，同样由父节点的 #address-cells确定此物理地址所占用的字长。 |
| length | 子地址空间的长度，由父节点的 #size-cells确定此地址长度所占用的字长。 |
如果 ranges属性值为空值，说明子地址空间和父地址空间完全相同，不需要进行地址转换，对于我们所使用的 RK3568来说，子地址空间和父地址空间完全相同，因此会在 rk3568.dtsi中找到大量的值为空的 ranges属性，如下所示：
pinctrl: pinctrl {
compatible = "rockchip,rk3568-pinctrl";
rockchip,grf = <&grf>;
rockchip,pmu = <&pmugrf>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
}
7. name属性
name属性值为字符串， name属性用于记录节点名字， name属性已经被弃用，不推荐使用name属性，一些老的设备树文件可能会使用此属性。
8. device_type属性
device_type属性值为字符串， IEEE 1275会用到此属性，用于描述设备的 FCode，但是设备树没有 FCode，所以此属性也被抛弃了。此属性只能用于 cpu节点或者 memory节点。rk3568.dtsi的 cpu0节点用到了此属性，内容如下所示：
3.4 根节点compatible属性
每个节点都有 compatible属性，根节点“ /”也不例外，在 rk3568-atk-evb1-ddr4-v10.dtsi文件中根节点的 compatible属性内容如下所示：
model = "Rockchip RK3568 ATK EVB1 DDR4 V10 Board";
compatible = "rockchip,rk3568-evb1-ddr4-v10", "rockchip,rk3568";
可以看出， compatible有两个值：“ rockchip,rk3568-evb1-ddr4-v10”和 rockchip,rk3568”。前面我们说了，设备节点的 compatible属性值是为了匹配 Linux内核中的驱动程序，那么根节点中的 compatible属性是为了做什么工作的？
通过根节点的 compatible属性可以知道我们所使用的设备，一般第一个值描述了所使用的硬件设备名字，比如这里使用的是“ rk3568-evb1-ddr4-v10”这个设备，第二个值描述了设备所使用的 SOC，比如这里使用的是 RK3568”
这颗SOC。 Linux内核会通过根节点的 compoatible属性查看是否支持此设备，如果支持的话设备就会启动 Linux内核。
include/linux/rockchip/cpu.h文件，有如下内容：
static inline bool cpu_is_rk3568(void)
{
if (rockchip_soc_id)
return (rockchip_soc_id & ROCKCHIP_CPU_MASK) == ROCKCHIP_CPU_RK3568;
return of_machine_is_compatible("rockchip,rk3568");
}
函数 cpu_is_rk3568用于判断当前是否为 RK3568，第 168行使用of_machine_is_compatible函数判断根节点 compatible值里面是否有“rockchip,rk3568”。根据 示例代码 8.3.4.1可知，根节点的 compatible中有“ rockchip,rk3568”，所以匹配。
3.5 向节点追加或修改内容
产品开发过程中可能面临着频繁的需求更改，比如第一版硬件上有一个 IIC接口的六轴芯片 MPU6050，第二版硬件又要把这个 MPU6050更换为 MPU9250等。一旦硬件修改了，我们就要同步的修改设备树文件，毕竟设备树是描述板子硬件信息的文件。假设现在有个六轴芯片fxls8471 fxls8471要接到 ATK-DLRK3568开发板的 I2C5接口上，那么相当于需要在 i2c5这个节点上添加一个 fxls8471子节点。先看一下 I2C5接口对应的节点，打开文件 rk3568.dtsi文件，找到如下所示内容：
i2c5: i2c@fe5e0000 {
compatible = "rockchip,rk3399-i2c";
reg = <0x0 0xfe5e0000 0x0 0x1000>;
clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>;
clock-names = "i2c", "pclk";
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&i2c5m0_xfer>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
上述代码就是 RK3568的 i2c5节点，现在要在 i2c5节点下创建一个子节点，这个
子节点就是 fxls8471，最简单的方法就是在 i2c5下直接添加一个名为 fxls8471的子节点，如下：
i2c5: i2c@fe5e0000 {
compatible = "rockchip,rk3399-i2c";
reg = <0x0 0xfe5e0000 0x0 0x1000>;
clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>;
clock-names = "i2c", "pclk";
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&i2c5m0_xfer>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
fxls8471@1e{
compatible="fsl,fxls8471";
reg=<0x1e>;
}
};
i2c5节点是定义 rk3568.dtsi文件中的，而 rk3568.dtsi是共有的设备树头文件，其他所有使用到 rk3568这颗 SOC的板子都会引用 rk3568.dtsi这个文件。直接在 i2c5节点中添加 fxls8471就相当于在其他的所有板子上都添加了 fxls8471这个设备，但是其他的板子并没有这个设备!
所以，需要追加节点，所以在rk3568-atk-evb1-ddr4-v10.dtsi文件中完成数据追加的内容，代码如下
&i2c5{
status="okey";
clock-frequency=<400000>;
fxls8471@1e{
compatible="fsl,fxls8471";
reg=<0x1e>;
};
}
4. 设备树在系统中的体现
Linux内核启动的时候会解析设备树中各个节点的信息，并且在根文件系统的 /proc/device-tree目录下根据节点名字创建不同文件夹，如图
5. 特殊节点
在根节点“ /”中有两个特殊的子节点 aliases和 chosen
5.1 aliases 子节点
rk3568.dtsi文件中aliases节点内容如下：
aliases {
csi2dphy0 = &csi2_dphy0;
csi2dphy1 = &csi2_dphy1;
csi2dphy2 = &csi2_dphy2;
dsi0 = &dsi0;
dsi1 = &dsi1;
ethernet0 = &gmac0;
ethernet1 = &gmac1;
gpio0 = &gpio0;
gpio1 = &gpio1;
gpio2 = &gpio2;
gpio3 = &gpio3;
gpio4 = &gpio4;
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c4;
i2c5 = &i2c5;
mmc0 = &sdhci;
mmc1 = &sdmmc0;
mmc2 = &sdmmc1;
mmc3 = &sdmmc2;
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
serial3 = &uart3;
serial4 = &uart4;
serial5 = &uart5;
serial6 = &uart6;
serial7 = &uart7;
serial8 = &uart8;
serial9 = &uart9;
spi0 = &spi0;
spi1 = &spi1;
spi2 = &spi2;
spi3 = &spi3;
spi4 = &sfc; // for U-Boot
};
单词 aliases的意思是“别名”，因此 aliases节点的主要功能就是定义别名，定义别名的目的就是为了方便访问节点。不过我们一般会在节点命名的时候会加上 label，然后通过 &label来访问节点，这样也很方便，而且设备树里面大量的使用 &label的形式来访问节点。
5.2 chosen子节点
chosen并不是一个真实的设备， chosen节点主要是为了 uboot向 Linux内核传递数据，重点是 bootargs参数。一般 .dts文件中 chosen节点通常为空或者内容很少， rk3568-linux.dtsi中chosen节点内容如下所示：
chosen chosen{
bootargs = "earlycon=uart8250,mmio32,0xfe660000console=ttyFIQ0root=PARTUUID=614e0000 0000 rw rootwait"
}
6. 绑定信息文档
设备树是用来描述板子上的设备信息的，不同的设备其信息不同，反映到设备树中就是属性不同。那么我们在设备树中添加一个硬件对应的节点的时候从哪里查阅相关的说明呢？在Linux内核源码中有详细的 TXT文档描述了如何添加节点，这些 TXT文档叫做绑定文档，路径为： Linux源码目录 /Documentation/devicetree/bindings
比如我们现在要想在 RK3568这颗 SOC的 I2C下添加一个节点，那么就可以查看Documentation/devicetree/bindings/i2c/i2c-rk3x.txt，此文档详细的描述了 瑞芯微出品 的 SOC如何在设备树中添加 I2C设备节点，文档内容如下所示：
* Rockchip RK3xxx I2C controller
This driver interfaces with the native I2C controller present in Rockchip
RK3xxx SoCs.
Required properties :
- reg : Offset and length of the register set for the device
- compatible: should be one of the following:
- "rockchip,rv1108-i2c": for rv1108
- "rockchip,rv1126-i2c": for rv1126
- "rockchip,rk3066-i2c": for rk3066
- "rockchip,rk3188-i2c": for rk3188
- "rockchip,rk3228-i2c": for rk3228
- "rockchip,rk3288-i2c": for rk3288
- "rockchip,rk3328-i2c", "rockchip,rk3399-i2c": for rk3328
- "rockchip,rk3399-i2c": for rk3399
- interrupts : interrupt number
- clocks: See ../clock/clock-bindings.txt
- For older hardware (rk3066, rk3188, rk3228, rk3288):
- There is one clock that's used both to derive the functional clock
for the device and as the bus clock.
- For newer hardware (rk3399): specified by name
- "i2c": This is used to derive the functional clock.
- "pclk": This is the bus clock.
Required on RK3066, RK3188 :
- rockchip,grf : the phandle of the syscon node for the general register
file (GRF)
- on those SoCs an alias with the correct I2C bus ID (bit offset in the GRF)
is also required.
Optional properties :
- clock-frequency : SCL frequency to use (in Hz). If omitted, 100kHz is used.
- i2c-scl-rising-time-ns : Number of nanoseconds the SCL signal takes to rise
(t(r) in I2C specification). If not specified this is assumed to be
the maximum the specification allows(1000 ns for Standard-mode,
300 ns for Fast-mode) which might cause slightly slower communication.
- i2c-scl-falling-time-ns : Number of nanoseconds the SCL signal takes to fall
(t(f) in the I2C specification). If not specified this is assumed to
be the maximum the specification allows (300 ns) which might cause
slightly slower communication.
- i2c-sda-falling-time-ns : Number of nanoseconds the SDA signal takes to fall
(t(f) in the I2C specification). If not specified we'll use the SCL
value since they are the same in nearly all cases.
Example:
aliases {
i2c0 = &i2c0;
}
i2c0: i2c@2002d000 {
compatible = "rockchip,rk3188-i2c";
reg = <0x2002d000 0x1000>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
rockchip,grf = <&grf>;
clock-names = "i2c";
clocks = <&cru PCLK_I2C0>;
i2c-scl-rising-time-ns = <800>;
i2c-scl-falling-time-ns = <100>;
};
7. 设备树常用OF操作函数
设备树描述了设备的详细信息，这些信息包括数字类型的、字符串类型的、数组类型的，我们在编写驱动的时候需要获取到这些信息。比如设备树使用 reg属性描述了某个外设的寄存器地址为 0X02005482，长度为 0X400，我们在编写驱动的时候需要获取到 reg属性的0X02005482和 0X400这两 个值，然后初始化外设。 Linux内核给我们提供了一系列的函数来获取设备树中的节点或者属性信息，这一系列的函数都有一个统一的前缀“ of_”，所以在很多资料里面也被叫做 OF函数。这些 OF函数原型都定义在 include/linux/of.h文件中。
7.1 查找节点的OF函数
Linux内核使用 device_node结构体来描述一个节点，此结构体定义在文件 include/linux/of.h中：
struct device_node {
const char *name;
const char *type;
phandle phandle;
const char *full_name;
struct fwnode_handle fwnode;
struct property *properties;
struct property *deadprops; /* removed properties */
struct device_node *parent;
struct device_node *child;
struct device_node *sibling;
#if defined(CONFIG_OF_KOBJ)
struct kobject kobj;
#endif
unsigned long _flags;
void *data;
#if defined(CONFIG_SPARC)
const char *path_component_name;
unsigned int unique_id;
struct of_irq_controller *irq_trans;
#endif
};
总共有5个查找函数
//函数通过节点名字查找指定的节点，函数原型如下：
struct device_node *of_find_node_by_name(struct device_node *from, const char *name);
//函数通过 device_type属性查找指定的节点，函数原型如下：
struct device_node *of_find_node_by_type(struct device_node *from, const char *type)
//函数根据 device_type和 compatible这两个属性查找指定的节点，
struct device_node *of_find_compatible_node(struct device_node *from, const char *type, const char *compat)
//函数通过 of_device_id匹配表来查找指定的节点，函数原
struct device_node *of_find_matching_node_and_match(struct device_node *from, const struct of_device_id *matches, const struct of_device_id **match)
//函数通过路径来查找指定的节点，函数原型如下：
inline struct device_node *of_find_node_by_path(const char *path)
7.2 找找父子节点的OF函数
//函数用于获取指定节点的父节点
struct device_node *of_get_parent(const struct device_node *node)
//迭代查找子节点
struct device_node *of_get_next_child(const struct device_node *node, struct device_node *prev)
7.3 提取属性值的OF函数
节点的属性信息里面保存了驱动所需要的内容，因此对于属性值的提取非常重要， Linux内核中使用结构体 property表示属性，此结构体同样定义在文件 include/linux/of.h中，内容如下：
struct property {
char *name;
int length;
void *value;
struct property *next;
#if defined(CONFIG_OF_DYNAMIC) || defined(CONFIG_SPARC)
unsigned long _flags;
#endif
#if defined(CONFIG_OF_PROMTREE)
unsigned int unique_id;
#endif
#if defined(CONFIG_OF_KOBJ)
struct bin_attribute attr;
#endif
};
提供的函数如下：
//查找指定的属性
struct property *of_find_property(const struct device_node *np, const char *name, int *lenp)
//获取属性中元素的数量
int of_property_count_elems_of_size(const struct device_node *np, const char *propname, int elem_size)
// 从属性中获取指定标号的u32类型数据值
int of_property_read_u32_index(const struct device_node *np, const char *propname, u32 index, u32 *out_value)
// 读取属性中u8类型的数组数据
int of_property_read_u8_array(const struct device_node *np, const char *propname, u8 *out_values, size_t sz)
// 读取属性中u16类型的数组数据
int of_property_read_u16_array(const struct device_node *np, const char *propname, u16 *out_values, size_t sz)
// 读取属性中u32类型的数组数据
int of_property_read_u32_array(const struct device_node *np, const char *propname, u32 *out_values, size_t sz)
// 读取属性中u64类型的数组数据
int of_property_read_u64_array(const struct device_node *np, const char *propname, u64 *out_values, size_t sz)
// 读取属性中u8类型的数据
int of_property_read_u8(const struct device_node *np, const char *propname, u8 *out_value)
// 读取属性中u16类型的数据
int of_property_read_u16(const struct device_node *np, const char *propname, u16 *out_value)
// 读取属性中u32类型的数据
int of_property_read_u32(const struct device_node *np, const char *propname, u32 *out_value)
// 读取属性中u64类型的数据
int of_property_read_u64(const struct device_node *np, const char *propname, u64 *out_value)
//读取属性中的字符串值
int of_property_read_string(struct device_node *np, const char *propname, const char **out_string)
//获取#address-cells的属性值
int of_n_addr_cells(struct device_node *np)
//获取#size-cells的属性值
int of_n_size_cells(struct device_node *np)
7.4 其他常用的OF函数
//函数用于查看节点的 compatible属性是否有包含 name指定的字符串，也即是检查设备节点的兼容性
int of_device_is_compatible(const struct device_node *device, const char *name)
//获取地址相关属性，主要是reg
const __be32 *of_get_address(struct device_node *dev, int index, u64 *size, unsigned int *flags)
//负责将设备树读取到的物理地址转换为虚拟地址
u64 of_translate_address(struct device_node *dev, const __be32 *addr)
//
int of_address_to_resource(struct device_node *dev, int index, struct resource *r)
//直接内存映射
void __iomem *of_iomap(struct device_node *np, int index) 函